EP2SGX130GF40C3ES vs EP2SGX130GF40C4NES 比較

詳細並排比較 EP2SGX130GF40C3ES 由 Altera 與 EP2SGX130GF40C4NES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP2SGX130GF40C3ES EP2SGX130GF40C4NES
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete 最後購買
Family Stratix II GX Stratix II GX
Series EP2SGX130 —
Logic Elements 132,540 132,540
Adaptive Logic Modules (ALMs) [DATA_NEEDED: ALM count] —
Logic Array Blocks (LABs) 7,047 —
Embedded Memory (TriMatrix) 6,747 Kbits —
DSP Blocks Up to 17 Yes (variable, see datasheet)
High-Speed Transceiver Channels 4 to 20 (per device variant) —
Transceiver Data Rate Up to 6.375 Gbps —
Global Clock Networks Up to 16 —
Regional Clock Networks Up to 32 per device region —
Internal Core Voltage 1.2 V —
Process Technology 90 nm CMOS 90 nm CMOS
Memory Controller Performance Up to 550 MHz (DDR/DDR2) —
DSP Multiplier Performance Up to 450 MHz —
封裝 FBGA-1508, 40 x 40 mm, 1.0 mm pitch (MS-034AAU-1) —
Operating Temperature Grade Commercial Extended (C3) —
安裝類型 Surface Mount (BGA) Surface Mount (flip-chip BGA)
RoHS 狀態 Lead-Free (per package marking MS-034AAU-1) —
Logic Blocks / ALMs — Approximately 53,000 ALMs
Core Voltage — 1.2 V
Maximum Transceiver Data Rate — 6.375 Gbps
Transceiver Channels — Up to 20 (4 to 20, device-dependent)
User I/O Pins — 734
Total Package Pins — 1508 (FC-FBGA ball grid)
Package Code — GF40 (FC-FBGA, 40x40 mm, 1.0 mm pitch)
Speed Grade — C4 (speed grade -4)
Internal Operating Frequency — Up to 717 MHz
Embedded Memory — Approximately 4.5 Mbits (TriMatrix)
PLL Blocks — 8
Lead-Free / RoHS — Yes (LEAD FREE per datasheet family code)
MSL 等級 — Per JEDEC J-STD-020, typically MSL-4 or higher [DATA_NEEDED: exact MSL level]
工作溫度 — Commercial Extended (per N suffix)
JEDEC Standard Reference — MS-034AAU-1

資料表與資源

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