EP2SGX130GF40C3NES vs EP2SGX130GF40C4ES 比較
詳細並排比較 EP2SGX130GF40C3NES 由 Altera 與 EP2SGX130GF40C4ES 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP2SGX130GF40C3NES - Stratix II GX FPGA, 132K LE, 6.375Gbps | Altera
EP2SGX130GF40C3NES Obsolete
規格比較
| 參數 | EP2SGX130GF40C3NES | EP2SGX130GF40C4ES |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Unknown |
| Family | Stratix II GX | — |
| Logic Elements | 132540 | — |
| Logic Array Blocks (LABs) | 7047 | — |
| Maximum Internal Frequency | 778.82 MHz | — |
| Process Technology | 90 nm CMOS | — |
| Core Voltage | 1.2 V | — |
| Transceiver Channels | 4 to 20 (per device family configuration) | — |
| Maximum Transceiver Data Rate | 6.375 Gbps | — |
| Transceiver Feature | Embedded SERDES with Clock/Data Recovery (CRU) | — |
| 記憶體類型 | TriMatrix embedded memory (distributed RAM, block RAM, shift register) | — |
| 封裝 | 1508-ball FC-FBGA (40 x 40 mm, 1 mm pitch) | — |
| Operating Temperature Grade | Commercial Extended | — |
| Terminal Form | Ball (BGA) | — |
| 安裝類型 | Surface Mount | Surface mount |
| RoHS 狀態 | Lead-free compliant (per package code MS-034AAU-1) | — |
| Series | EP2SGX130 | — |
| Product Type | — | Field-programmable gate array (FPGA) |
| Product Family | — | Stratix II GX |
| Logic Cells | — | 132,540 |
| Configurable Logic Blocks | — | 7,047 CLBs |
| Logic Technology | — | CMOS |
| User I/O | — | 734 I/O |
| Internal Frequency | — | 717 MHz |
| Supply Voltage Range | — | 1.15 V to 1.25 V |
| Package Pin Count | — | 1,508 pins |
| Package Type | — | FBGA-1508 |
| Package Body Size | — | 40 mm by 40 mm |
| Ball Pitch | — | 1 mm |
| Package Designation | — | MS-034AAU-1 |
| Lead-Free | — | Yes |
| 工作溫度範圍 | — | [DATA_NEEDED: operating temperature range] |
| Transceiver Count | — | [DATA_NEEDED: transceiver count] |
| Configuration Memory Type | — | [DATA_NEEDED: configuration memory type] |