EP2SGX60EF1152I4N vs EP2SGX60FF1152 比較
詳細並排比較 EP2SGX60EF1152I4N 由 Intel 與 EP2SGX60FF1152 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP2SGX60EF1152I4N | EP2SGX60FF1152 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 最後購買 |
| Device Type | FPGA | — |
| Product Family | Stratix II GX | — |
| Logic Cells | 60,440 | — |
| Embedded Memory | 2,544,192 bits | 2,544,192 bits |
| I/O Count | 534 | — |
| Internal Frequency | 717 MHz | — |
| 供應電壓 | 1.2 V | — |
| 封裝 | 1,152-ball FBGA | 1152-BBGA, FineLine BGA (FF1152) |
| Package Type | Other, 23 x 23 mm, 1 mm pitch, MS-034AAJ-1, FBGA-484 | — |
| Pins | 484 | — |
| Device Technology | 90 nm | — |
| Logic Blocks | 3,022 LABs | — |
| 安裝類型 | Surface mount | Surface Mount |
| Operating Temperature Grade | Industrial | — |
| Compliance | [DATA_NEEDED: compliance certification details] | — |
| Transceiver Count | [DATA_NEEDED: high-speed transceiver count] | — |
| Configuration Memory | [DATA_NEEDED: configuration memory specification] | — |
| Package Pinout | [DATA_NEEDED: complete ball-map pinout] | — |
| Series | — | Stratix II GX |
| Family | — | Stratix II GX FPGA |
| Logic Elements | — | 60,440 |
| DSP Blocks (18x18 Multipliers) | — | 192 (16 blocks) |
| Maximum User I/O | — | 364 |
| Number of LABs/CLBs | — | 3022 |
| Transceivers | — | 12 channels up to 3.125 Gbps |
| 工作溫度 | — | -40C to +85C (industrial) |
| Voltage - Supply | — | 1.2 V core / multiple VCCIO rails |
| Process Technology | — | 90 nm CMOS, SRAM-based |
| Configuration Method | — | JTAG IEEE 1149.1, Serial, Passive Parallel, Fast Passive Parallel |
| RoHS 狀態 | — | Compliant |