EP3C80F484C6N vs EP3C80F484C7 比較
詳細並排比較 EP3C80F484C6N 由 Altera 與 EP3C80F484C7 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP3C80F484C6N | EP3C80F484C7 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | Unknown |
| Series | Cyclone III | — |
| Family | Cyclone III FPGA (Low Power) | Cyclone III |
| Logic Elements (LE) | 81,264 | — |
| Embedded Memory Bits | 2,810,880 (4 Mbits) | — |
| Maximum User I/O | 295 | — |
| 封裝 | 484-ball FBGA (FineLine BGA), 23x23 mm, 1.0 mm pitch | 484-BGA |
| 安裝類型 | Surface Mount (SMT) | Surface Mount |
| Number of PLLs | 4 | — |
| Number of Global Clock Networks | 20 | — |
| Embedded 18x18 Multipliers | 244 | — |
| Process Technology | 65 nm TSMC low-power CMOS | — |
| Core Voltage (VCCINT) | 1.2 V | — |
| I/O Voltage (VCCIO) | 1.2V / 1.5V / 1.8V / 2.5V / 3.3V (per-bank) | — |
| 工作溫度 | 0C to +85C (Commercial, 'C' speed grade) | — |
| Speed Grade | 6 (medium speed bin) | — |
| Configuration Scheme | Active Serial (AS), Passive Serial (PS), JTAG, Fast Passive Parallel (FPP) | — |
| RoHS 狀態 | Compliant (Pb-free) | [DATA_NEEDED: RoHS status] |
| Device Type | — | Field Programmable Gate Array (FPGA) |
| Logic Cells | — | 81264 cells |
| Memory | — | 2810880 bit |
| User I/O | — | 295 I/O |
| Logic Array Blocks | — | 5079 LABs |
| Technology | — | 65 nm |
| Stated Frequency | — | 437.5 MHz |
| 供應電壓 | — | 1.2 V |
| 腳位數 | — | 484 pins |
| Configuration | — | FPGA programmable after assembly |
| REACH Status | — | [DATA_NEEDED: REACH status] |
| AEC-Q100 Qualification | — | [DATA_NEEDED: AEC-Q100 qualification] |