EP3SE260H780C2 vs EP3SE260H780C3N 比較

詳細並排比較 EP3SE260H780C2 由 Altera 與 EP3SE260H780C3N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

Altera
EP3SE260H780C2 EP3SE260H780C2 - Stratix III E 260K LE FPGA | Altera | 780-BGA

EP3SE260H780C2 - Stratix III E 260K LE FPGA | Altera | 780-BGA

EP3SE260H780C2 ⚠ 最後購買機會

規格比較

參數 EP3SE260H780C2 EP3SE260H780C3N
品牌 Altera Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 最後購買 啟用中
Family Stratix® III E —
Series Stratix III Stratix® III E
Logic Elements (LE) 255,000 255,000
Adaptive Logic Modules (ALM) 102,000 —
Embedded Memory (bits) 16,672,768 16,672,768
User I/Os 488 488
Number of LABs/CLBs 10,200 10,200
Process Node 65 nm —
Core Voltage 0.86 V to 1.15 V —
封裝 780-BBGA, FCBGA 780-BBGA, FCBGA (H780)
安裝類型 Surface Mount Surface Mount
工作溫度 0C to +85C (Commercial) 0 °C to +85 °C (C grade, commercial)
RoHS 狀態 Compliant Compliant (lead-free 'N' suffix)
Lead Free Yes —
MSL 等級 3 (per JEDEC J-STD-020) —
Number of Pins / Balls — 780
Process Technology — 40 nm CMOS
Maximum Core Frequency — [DATA_NEEDED: maximum core frequency MHz]
Supply Voltage (VCCINT) — [DATA_NEEDED: VCCINT nominal V]
Transceivers — [DATA_NEEDED: number of embedded transceivers and max data rate]
DSP Blocks — [DATA_NEEDED: number of DSP blocks and precision]
濕度敏感等級 (MSL) — [DATA_NEEDED: MSL level per JEDEC J-STD-020]
Configuration Method — SRAM-based, configured via JTAG / passive / active serial / fast passive parallel
Design Toolchain — Altera Quartus II (legacy); Intel Quartus Prime

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