EP3SE260H780C3N vs EP3SE260F1517I4N 比較
詳細並排比較 EP3SE260H780C3N 由 Intel 與 EP3SE260F1517I4N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP3SE260H780C3N | EP3SE260F1517I4N |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 最後購買 |
| Series | Stratix® III E | Stratix III E |
| Logic Elements (LE) | 255,000 | — |
| Embedded Memory (bits) | 16,672,768 | — |
| Number of LABs/CLBs | 10,200 | — |
| User I/Os | 488 | — |
| Number of Pins / Balls | 780 | — |
| 封裝 | 780-BBGA, FCBGA (H780) | 1517-BBGA, FCBGA |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| 工作溫度 | 0 °C to +85 °C (C grade, commercial) | -40 °C to +100 °C (Industrial) |
| Process Technology | 40 nm CMOS | TSMC 65 nm |
| Maximum Core Frequency | [DATA_NEEDED: maximum core frequency MHz] | — |
| Supply Voltage (VCCINT) | [DATA_NEEDED: VCCINT nominal V] | — |
| Transceivers | [DATA_NEEDED: number of embedded transceivers and max data rate] | [DATA_NEEDED: number of full-duplex channels] |
| DSP Blocks | [DATA_NEEDED: number of DSP blocks and precision] | [DATA_NEEDED: number of 18x18 multipliers] |
| RoHS 狀態 | Compliant (lead-free 'N' suffix) | — |
| 濕度敏感等級 (MSL) | [DATA_NEEDED: MSL level per JEDEC J-STD-020] | — |
| Configuration Method | SRAM-based, configured via JTAG / passive / active serial / fast passive parallel | — |
| Design Toolchain | Altera Quartus II (legacy); Intel Quartus Prime | — |
| Logic Elements | — | 255,000 |
| Embedded Memory Bits | — | 16,672,768 bits |
| Embedded Memory (M9K/M144K blocks) | — | [DATA_NEEDED: total Kbits and block count] |
| User I/O Pins | — | 976 |
| Transceiver Data Rate | — | 600 Mbps to 6.375 Gbps |
| PLLs | — | [DATA_NEEDED: total PLL count] |
| Core Voltage | — | 1.1 V |
| Package Body Size | — | [DATA_NEEDED: mm x mm] |
| Operating Temperature Grade | — | Industrial (I4) |
| Lead-Free / RoHS | — | [DATA_NEEDED: explicit RoHS statement] |
| MSL 等級 | — | [DATA_NEEDED: MSL classification] |