EP3SE50F484I3N vs EP3SE50F484I4N 比較

詳細並排比較 EP3SE50F484I3N 由 Intel 與 EP3SE50F484I4N 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP3SE50F484I3N EP3SE50F484I4N
品牌 Intel Intel
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND NRND
Family Stratix III E —
Logic Elements 47,500 —
Number of LABs 1,900 —
Total Memory Bits 5,760,000 —
Maximum User I/O 296 —
Number of I/O Banks [DATA_NEEDED: number of I/O banks] —
Core Voltage VCC 0.9 V —
Auxiliary Voltage VCCAUX 1.1 V —
Process Technology 65 nm 65 nm CMOS
Maximum Internal Frequency 500 MHz —
Speed Grade I3 (industrial, bin 3) I4
工作溫度 -40C to +100C (industrial) 0 C to +85 C (Industrial)
封裝 484-pin FC-FBGA (flip-chip BGA) 484-ball FC-FBGA (F484)
安裝類型 Surface Mount (BGA) —
Lead-Free / RoHS Yes (N suffix) Lead-free (per ampheo listing)
Configuration Method Active serial (AS), passive serial (PS), JTAG, fast passive parallel (FPP) —
DSP Blocks [DATA_NEEDED: number of DSP blocks] —
Embedded Multipliers (18x18) [DATA_NEEDED: number of 18x18 multipliers] 384
Transceiver Count [DATA_NEEDED: number of embedded transceivers] —
Device Family — Stratix III E
Logic Elements (LE) — 47,500
Adaptive Logic Modules (ALMs) — 19,000
Logic Array Blocks (LABs) — 1,900
Embedded Memory (TriMatrix) — 2,136 Kbits
User I/Os — 296
I/O Banks — 12
PLLs — 8
Global Clock Networks — 16
Maximum User I/O Frequency — 800 MHz (per DigChip datasheet summary)
Core Voltage — 1.1 V

資料表與資源

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