EP3SL200H780C3N vs EP3SL200H780C3 比較
詳細並排比較 EP3SL200H780C3N 由 Intel 與 EP3SL200H780C3 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP3SL200H780C3N | EP3SL200H780C3 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | Stratix III L (low-power) | — |
| Process Node | 40 nm | — |
| Logic Elements | 200,000 | 200,000 |
| Embedded Memory Bits | 10,901,504 bits | 10,901,520 |
| Logic Array Blocks (LABs) | 8,000 | 8,000 |
| User I/Os | 488 | — |
| 封裝 | 780-Ball FCBGA (HBGA), 29 x 29 mm | 780-ball FCBGA (H780) |
| 安裝類型 | Surface Mount | Surface Mount (BGA) |
| Maximum Internal Clock Frequency | 800 MHz | — |
| Transceivers | 24 channels, up to 3.75 Gbps | [DATA_NEEDED: count and speed] |
| DSP Blocks | 384 | [DATA_NEEDED: count] |
| Speed Grade | C3 (commercial, -3 speed) | 3 (slowest of Stratix III bins) |
| 工作溫度 | 0C to +85C (commercial) | Commercial grade (0C to +85C, exact range [DATA_NEEDED]) |
| Voltage - Core | 0.9 V / 1.0 V (core, VCC) | — |
| Voltage - I/O | 1.2 V to 3.3 V (VCCIO banks) | — |
| MSL 等級 | 3 | 3 (168 Hours) |
| Lead-Free / RoHS | Yes | — |
| Mounting Pitch | 1.0 mm ball pitch | — |
| PLLs | 12 (Stratix III PLL array) | — |
| Configuration | JTAG IEEE Std 1149.1, passive/active serial | — |
| Manufacturer | — | Intel (formerly Altera) |
| Series | — | Stratix III L |
| Device | — | EP3SL200 |
| User I/O Pins | — | 488 |
| Sub-Family | — | Stratix III L (lower-power logic variant) |
| RoHS 狀態 | — | [DATA_NEEDED: confirmed in datasheet] |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED] |