EP3SL50F484I4L vs EP3SL50F484I4LN 比較

詳細並排比較 EP3SL50F484I4L 由 Intel 與 EP3SL50F484I4LN 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP3SL50F484I4L EP3SL50F484I4LN
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND Obsolete
Series Stratix III L (Low Power) —
Family Stratix III —
Logic Elements (LE) 47,500 —
Embedded Memory Bits 2,184,192 bits (~273 KB) —
User I/O Pins 296 —
封裝 484-ball FBGA (FCBGA) 484-BBGA, FCBGA
Speed Grade 4 —
工作溫度 0 °C to 85 °C (commercial, per DigiKey listing) —
供應電壓 0.9 V core (family-typical) —
Process Technology 65 nm low-power CMOS CMOS
安裝類型 Surface Mount —
Lead-Free / RoHS Yes (RoHS compliant) —
Configuration Modes Passive Serial, Fast Passive Parallel, JTAG —
Transceivers Family supports up to 4 transceivers per family datasheet —
DSP Blocks Family supports up to 384 18x18 multipliers (family-level) —
Product Type — Field Programmable Gate Array (FPGA)
Device Family — Stratix III L
Logic Cells — 47,500
Embedded Memory — 2,184,192 bits
User I/O — 296
Logic Array Blocks — 1,900 LABs
Listed Frequency — 717 MHz
Package Description — FBGA-484
Terminal Count — 484
Terminal Form — Ball
Package Body Material — Plastic/Epoxy
Lead-Free Status — Lead free
Operating Temperature Grade — Industrial
I/O Banks — [DATA_NEEDED: I/O bank count]
Transceiver Count — [DATA_NEEDED: transceiver count]
Core Voltage — [DATA_NEEDED: core voltage]
I/O Voltage — [DATA_NEEDED: I/O voltage]
Junction Temperature — [DATA_NEEDED: junction temperature]
RoHS 狀態 — [DATA_NEEDED: RoHS status]
REACH Status — [DATA_NEEDED: REACH status]
AEC-Q100 Qualification — [DATA_NEEDED: AEC-Q100 qualification]

資料表與資源

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