EP610DC-15 vs EP610IDC-15 比較
詳細並排比較 EP610DC-15 由 Altera 與 EP610IDC-15 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610DC-15 | EP610IDC-15 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Product Family | Classic EPLD (EP610) | — |
| Architecture | UV-erasable CMOS PAL-type | — |
| Macrocells | 16 | 16 |
| Logic Expanders | 4 | — |
| Dedicated Inputs | 20 | — |
| Bidirectional I/O Pins | 16 | — |
| Total Product Terms | 160 | — |
| Propagation Delay (tPD) | 15 ns (speed grade -15) | 15 ns |
| Maximum Internal Clock Frequency | 71.4 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.75 V to 5.25 V (5 V nominal) |
| 工作溫度 | 0C to 70C (commercial) | 0C to +70C (commercial) |
| 封裝 | 24-pin Ceramic DIP (CDIP-24) with UV window | 24-pin CerDIP (ceramic DIP) |
| 安裝類型 | Through-Hole | Through-hole |
| Programming Method | JEDEC fuse map, UV erasure | — |
| Technology | CMOS | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status of CerDIP variant] |
| Device Family | — | Altera Classic EPLD |
| Usable Gates | — | 300 |
| Maximum Frequency | — | 66 MHz |
| Process Technology | — | CMOS, UV-erasable / OTP |
| I/O Pins | — | 24 (per package; macrocell-programmable) |
| Logic-Block Architecture | — | AND/OR macrocell array with programmable flip-flops |
| Program/Erase | — | UV-erasable, OTP-compatible |
| Development Tool | — | MAX+PLUS II |
| Programming Current | — | 11.0 mA typical (per Classic family datasheet) |