EP610DC-20 vs EP610DI-30 比較
詳細並排比較 EP610DC-20 由 Intel 與 EP610DI-30 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP610DI-30 - 16-Macrocell Classic EPLD, 30ns, CERDIP-24 | Rochester Electronics
EP610DI-30 ✓ 啟用中規格比較
| 參數 | EP610DC-20 | EP610DI-30 |
|---|---|---|
| 品牌 | Intel | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 啟用中 |
| Product Type | CMOS UV-Erasable Programmable Logic Device (EPLD) | — |
| Family | Classic EP610 | Classic EP610 |
| Logic Macrocells | 16 | — |
| Dedicated Inputs | 4 | — |
| I/O Pins | 16 (bidirectional) | [DATA_NEEDED: I/O pin count] |
| Total Usable Pins | 20 | — |
| Product Terms (p-terms) | 160 | — |
| Propagation Delay (tPD) | 22 ns | 30 ns |
| Maximum Toggle Frequency (fMAX) | 55.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| 工作溫度 | 0 °C to 70 °C (commercial) | [DATA_NEEDED: operating temperature range] |
| 封裝 | 24-pin Ceramic DIP (CDIP-24) with UV window | CERDIP-24 (windowed, UV-erasable) |
| Programming Method | UV erasure + parallel programmer | — |
| Process Technology | CMOS, UV-erasable floating gate | — |
| 安裝類型 | Through-hole | Through-Hole |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | unknown |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| Pipelined Data Rate | — | 100 MHz |
| Technology | — | CMOS |
| 供應電壓 | — | 5 V (single supply) |
| Programmable Elements | — | EPROM (UV-erasable, windowed) |
| Logic Capacity | — | [DATA_NEEDED: usable gates / logic capacity] |
| Original Manufacturer | — | Altera (now Intel) |
| Current Supplier | — | Rochester Electronics (authorized continuing source) |
| MSL 等級 | — | N/A (through-hole, non-surface-mount) |