EP610DC-25 vs EP610DC-10 比較
詳細並排比較 EP610DC-25 由 Rochester Electronics 與 EP610DC-10 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ 啟用中規格比較
| 參數 | EP610DC-25 | EP610DC-10 |
|---|---|---|
| 品牌 | Rochester Electronics | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | Obsolete |
| Family | Altera Classic EPLD | — |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Macrocells | 16 | 16 |
| Equivalent Gates | 300 | — |
| Maximum Propagation Delay (tPD) | 25 ns | — |
| Pipelined Data Rate | Up to 100 MHz | — |
| Number of I/O Pins | 22 | — |
| Number of Dedicated Inputs | 4 | — |
| Total Pin Count | 24 | — |
| 封裝 | 24-pin CDIP (Ceramic DIP, through-hole) | 24-pin CDIP (Ceramic DIP, windowed) |
| 安裝類型 | Through Hole | Through-Hole |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| 工作溫度 | 0 C to +70 C | 0C to +70C (commercial) |
| Technology | CMOS EPROM (UV-erasable) | CMOS, EPROM-based (UV-erasable) |
| Programming Method | JEDEC fuse-map / UV-erase | — |
| Speed Grade Suffix | -25 (25 ns tPD) | — |
| Device Family | — | Altera Classic EPLD |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | — | 10 ns |
| Speed Grade | — | -10 |
| 供應電壓 | — | 5 V (single supply) |
| I/O Pins | — | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| Logic Elements | — | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | — | UV-erasable EPROM |
| Reprogrammable | — | Yes (UV erase window on package) |
| RoHS 狀態 | — | [DATA_NEEDED: not stated in verified web data] |