EP610DI-25 vs EP610DC-20 比較
詳細並排比較 EP610DI-25 由 Intel 與 EP610DC-20 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610DI-25 | EP610DC-20 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Part Family | Classic EPLD | — |
| Macrocells | 16 | — |
| Propagation Delay (tPD) | 25 ns | 22 ns |
| Maximum Pipelined Clock Frequency | 100 MHz (max fCNT, per family datasheet) | — |
| I/O Pins | 16 (bidirectional) | 16 (bidirectional) |
| Dedicated Inputs | 4 | 4 |
| Total User I/O | 20 | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Supply Voltage (VCC) | 5 V nominal | 4.75 V to 5.25 V (5 V nominal) |
| Package Type | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 | — |
| 腳位數 | 24 | — |
| 安裝類型 | Through-Hole (DIP) | Through-hole |
| 工作溫度 | Industrial (per "I" suffix) | 0 °C to 70 °C (commercial) |
| Speed Grade Suffix | 25 = 25 ns | — |
| Compliance | RoHS status unknown (legacy 1990s part) | — |
| Product Type | — | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Family | — | Classic EP610 |
| Logic Macrocells | — | 16 |
| Total Usable Pins | — | 20 |
| Product Terms (p-terms) | — | 160 |
| Maximum Toggle Frequency (fMAX) | — | 55.6 MHz |
| 封裝 | — | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Programming Method | — | UV erasure + parallel programmer |
| Process Technology | — | CMOS, UV-erasable floating gate |
| RoHS 狀態 | — | [DATA_NEEDED: RoHS compliance status] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |