EP610DI-30N vs EP610DC-25 比較
詳細並排比較 EP610DI-30N 由 Altera 與 EP610DC-25 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP610DC-25 - 16-Macrocell Classic EPLD, 25ns tPD, CDIP-24 | Rochester
EP610DC-25 ✓ 啟用中規格比較
| 參數 | EP610DI-30N | EP610DC-25 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 啟用中 |
| Product Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EP610 | Altera Classic EPLD |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Propagation Delay (tPD) | 30 ns | — |
| Maximum Frequency | 33.3 MHz (system); 100 MHz (pipelined) | — |
| Supply Voltage (VCC) | 5 V ±5% | 4.75 V to 5.25 V (5 V nominal) |
| 封裝 | CDIP-24 (Ceramic DIP, windowed) | 24-pin CDIP (Ceramic DIP, through-hole) |
| 腳位數 | 24 | — |
| 工作溫度 | -40°C to +85°C (industrial) | 0 C to +70 C |
| Process Technology | CMOS | — |
| Programming Method | UV-erasable (windowed ceramic) | JEDEC fuse-map / UV-erase |
| 安裝類型 | Through-hole (DIP) | Through Hole |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | — |
| Equivalent Gates | — | 300 |
| Maximum Propagation Delay (tPD) | — | 25 ns |
| Pipelined Data Rate | — | Up to 100 MHz |
| Number of I/O Pins | — | 22 |
| Number of Dedicated Inputs | — | 4 |
| Total Pin Count | — | 24 |
| Technology | — | CMOS EPROM (UV-erasable) |
| Speed Grade Suffix | — | -25 (25 ns tPD) |