EP610DI-35 vs EP610DI-25 比較
詳細並排比較 EP610DI-35 由 Intel 與 EP610DI-25 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP610DI-35 - 16-Macrocell Classic EPLD, 35ns, 5V, 24-CDIP | Intel / Altera
EP610DI-35 Obsolete
規格比較
| 參數 | EP610DI-35 | EP610DI-25 |
|---|---|---|
| 品牌 | Intel | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | — |
| Series | EP610 | — |
| Logic Cells / Macrocells | 16 macrocells | — |
| Usable Gates | 300 | — |
| Product Terms | 160 | — |
| I/O Pins | 16 bidirectional | 16 (bidirectional) |
| Total Inputs | 20 (including 4 dedicated inputs) | — |
| Propagation Delay (tpd) | 35 ns | — |
| Maximum Toggle Frequency | 28.6 MHz | — |
| Internal Pipelined Data Rate | Up to 100 MHz | — |
| 供應電壓 | 5 V | — |
| Technology | CMOS, UV-erasable | CMOS EPROM (UV-erasable) |
| 封裝 | 24-pin CDIP (Ceramic DIP) | — |
| 安裝類型 | Through-hole | Through-Hole (DIP) |
| 工作溫度 | [DATA_NEEDED: industrial/commercial grade range] | Industrial (per "I" suffix) |
| RoHS 狀態 | [DATA_NEEDED: not confirmed in supplied web data] | — |
| Part Family | — | Classic EPLD |
| Macrocells | — | 16 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Pipelined Clock Frequency | — | 100 MHz (max fCNT, per family datasheet) |
| Dedicated Inputs | — | 4 |
| Total User I/O | — | 20 |
| Supply Voltage (VCC) | — | 5 V nominal |
| Package Type | — | Ceramic DIP, glass-sealed (windowed), R-GDIP-T24 |
| 腳位數 | — | 24 |
| Speed Grade Suffix | — | 25 = 25 ns |
| Compliance | — | RoHS status unknown (legacy 1990s part) |