EP610DM-35 vs EP610DI-35 比較
詳細並排比較 EP610DM-35 由 Altera 與 EP610DI-35 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Intel
EP610DI-35 - 16-Macrocell Classic EPLD, 35ns, 5V, 24-CDIP | Intel / Altera
EP610DI-35 Obsolete規格比較
| 參數 | EP610DM-35 | EP610DI-35 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Manufacturer | Altera (Rochester Electronics authorized stock) | — |
| Part Family | Classic EPLD | — |
| Logic Family | PAL-type EPLD, CMOS, UV-erasable | — |
| Number of Macrocells | 16 | — |
| Number of Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Pipelined Data Rate (fMAX) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| 封裝 | 24-pin CDIP (CERDIP) with UV window | 24-pin CDIP (Ceramic DIP) |
| Temperature Grade (M) | Military -55°C to +125°C | — |
| I/O Pins | 24 dedicated I/O (input + bidirectional) | 16 bidirectional |
| Programmability | UV-erasable, reprogrammable | — |
| 工作溫度範圍 | -55°C to +125°C | — |
| MSL 等級 | [DATA_NEEDED: MSL rating] | — |
| RoHS 狀態 | Non-compliant (contains lead, hermetic CERDIP) | [DATA_NEEDED: not confirmed in supplied web data] |
| Family | — | Altera Classic EPLD |
| Series | — | EP610 |
| Logic Cells / Macrocells | — | 16 macrocells |
| Usable Gates | — | 300 |
| Product Terms | — | 160 |
| Total Inputs | — | 20 (including 4 dedicated inputs) |
| Propagation Delay (tpd) | — | 35 ns |
| Maximum Toggle Frequency | — | 28.6 MHz |
| Internal Pipelined Data Rate | — | Up to 100 MHz |
| 供應電壓 | — | 5 V |
| Technology | — | CMOS, UV-erasable |
| 安裝類型 | — | Through-hole |
| 工作溫度 | — | [DATA_NEEDED: industrial/commercial grade range] |