EP610DM-35 vs EP610ILI-12 比較
詳細並排比較 EP610DM-35 由 Altera 與 EP610ILI-12 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610DM-35 | EP610ILI-12 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Manufacturer | Altera (Rochester Electronics authorized stock) | — |
| Part Family | Classic EPLD | — |
| Logic Family | PAL-type EPLD, CMOS, UV-erasable | — |
| Number of Macrocells | 16 | — |
| Number of Gates | 300 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Pipelined Data Rate (fMAX) | 100 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| 封裝 | 24-pin CDIP (CERDIP) with UV window | 28-pin PLCC (J-Lead) |
| Temperature Grade (M) | Military -55°C to +125°C | — |
| I/O Pins | 24 dedicated I/O (input + bidirectional) | — |
| Programmability | UV-erasable, reprogrammable | — |
| 工作溫度範圍 | -55°C to +125°C | — |
| MSL 等級 | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| RoHS 狀態 | Non-compliant (contains lead, hermetic CERDIP) | [DATA_NEEDED: RoHS status] |
| Family | — | Classic EPLD (EP610) |
| Usable Gates | — | 300 |
| Macro Cells | — | 16 |
| Speed Grade (tpd) | — | 12 ns |
| Supply Voltage (Vcc) | — | 5 V (4.75 V to 5.25 V) |
| Supply Voltage (Vpp) | — | [DATA_NEEDED: Vpp programming voltage] |
| Operating Frequency (max) | — | 83.3 MHz |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| User I/O Pins | — | [DATA_NEEDED: I/O pin count] |
| Dedicated Inputs | — | 4 |
| Technology | — | CMOS EPROM |
| 工作溫度 | — | -40C to +85C (industrial grade) |
| 安裝類型 | — | Surface Mount |
| Programmable Security Bit | — | Yes |
| TTL Compatibility | — | 100 TTL emulation |