EP610ILC-10 vs EP610DC-10 比較
詳細並排比較 EP610ILC-10 由 Altera 與 EP610DC-10 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610ILC-10 | EP610DC-10 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | Classic EPLD | Altera Classic EPLD |
| Product Type | UV-Erasable / OTP PLD | — |
| Architecture | PAL-type with macrocells | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | — |
| Product Terms | 160 | — |
| I/O Pins | 16 | [DATA_NEEDED: exact I/O count for CDIP-24 variant] |
| Dedicated Inputs | 4 | — |
| 供應電壓 | 5 V (single supply) | 5 V (single supply) |
| Pin-to-Pin Delay (tPD) | 10 ns (grade -10) | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family Compatibility | TTL (5 V CMOS/TTL-compatible I/O) | — |
| 封裝 | PLCC-28 (plastic J-lead chip carrier) | 24-pin CDIP (Ceramic DIP, windowed) |
| 安裝類型 | Surface Mount (PLCC socket or solder) | Through-Hole |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: not stated in verified web data] |
| Maximum Pipelined Data Rate | — | 100 MHz |
| Pin-to-Pin Propagation Delay (tpd) | — | 10 ns |
| Speed Grade | — | -10 |
| Technology | — | CMOS, EPROM-based (UV-erasable) |
| Logic Elements | — | 16 macrocells (programmable AND/OR array) |
| Configuration Memory | — | UV-erasable EPROM |
| Reprogrammable | — | Yes (UV erase window on package) |