EP610IPC-25 vs EP610IPC-10 比較
詳細並排比較 EP610IPC-25 由 Intel 與 EP610IPC-10 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610IPC-25 | EP610IPC-10 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Classic EPLD (EP610) | Altera Classic EPLD |
| Architecture | PAL-type, CMOS, Erasable | Turbo-only AND-OR-NOT, PAL-type |
| Propagation Delay (tpd) | 25 ns (max) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Maximum Inputs | 20 | — |
| Maximum I/O Pins | 16 | — |
| Dedicated Outputs | 16 | — |
| Product Terms | 160 | 160 total |
| 工作溫度 | 0 °C to +70 °C (Commercial) | -40C to +85C (industrial) |
| 封裝 | 24-pin PDIP (Plastic DIP) | 24-pin PDIP (Plastic DIP) |
| Technology | CMOS, UV-erasable (windowless in IPC pkg) | CMOS EPROM (UV-erasable / OTP) |
| TTL Compatibility | 100% TTL emulation | — |
| 安裝類型 | Through-Hole | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| RoHS 狀態 | Non-compliant (contains Pb, PDIP package) | — |
| Logic Capacity | Equivalent to ~24 standard 24-pin PALs | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Programmable Gates | — | 300 usable gates |
| Macrocells | — | 16 |
| Maximum Operating Frequency | — | 100 MHz |
| Propagation Delay (tPD) | — | 15 ns (commerical -10 grade) |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 16 |
| Total Input Pins | — | 20 |
| 供應電壓 | — | 5 V |
| Programming Method | — | Altera programming hardware (UV erase for I grade, OTP for C grade) |
| TTL Emulation | — | 100% TTL compatible |