EP610PC-20 vs EP610PC25 比較
詳細並排比較 EP610PC-20 由 Altera 與 EP610PC25 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610PC-20 | EP610PC25 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD | — |
| Logic Elements | 16 macrocells | — |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 20 ns | 25 ns |
| Maximum Operating Frequency | 100 MHz (pipelined) | — |
| Supply Voltage (VCC) | 5 V ±10% | 5 V |
| 腳位數 | 24 | — |
| 封裝 | PDIP-24 | PDIP-24 |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Process Technology | CMOS EPROM | — |
| Programmable Flip-Flops | 16 | — |
| Input Pins | 24 | — |
| Output Pins | 16 | — |
| I/O Compatibility | TTL | — |
| Program/Erase Method | UV (windowed) or OTP | — |
| RoHS 狀態 | Non-compliant (legacy PDIP) | unknown |
| Device Family | — | Altera Classic EPLD |
| Logic Type | — | EPLD (Erasable Programmable Logic Device) |
| Macrocells | — | 16 |
| Pipelined Data Rate | — | Up to 100 MHz |
| Programming Voltage (VPP) | — | 12 V |
| ICC (typical) | — | 200 mA |
| 安裝類型 | — | Through-Hole |
| Programmability | — | One-Time-Programmable (OTP), UV-erasable variant exists |
| 腳位數 | — | 24 |
| Technology | — | 5 V CMOS |
| Lifecycle | — | Obsolete (last shipped ~2000s) |