EP610PC-20T vs EP910PC-20T 比較

詳細並排比較 EP610PC-20T 由 Intel 與 EP910PC-20T 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP610PC-20T EP910PC-20T
品牌 Intel Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 NRND Unknown
Family Classic EPLD Classic EPLD
Logic Elements / Macrocells 16 macrocells —
Usable Gates 300 gates —
Propagation Delay (tPD) 20 ns —
Maximum Frequency (fMAX) 62.5 MHz —
Pipelined Data Rate up to 100 MHz —
Supply Voltage (VCC) 5 V —
Number of Dedicated Inputs 16 —
Number of I/O Pins 16 —
Programmable Output Enable Yes (per macrocell) —
封裝 24-pin PDIP (Plastic DIP) —
安裝類型 Through-Hole —
工作溫度 0C to +70C (Commercial) [DATA_NEEDED: operating temperature range]
Programming Technology UV-erasable EPROM, CMOS —
Development Tool MAX+PLUS II —
RoHS 狀態 unknown unknown
Device Type — EPLD
Fabrication Technology — CMOS
Logic Integration — 300 to 900 usable gates
Logic Emulation — 100% TTL emulation
Application Function — High-speed, low-power logic integration
Programmable Device Class — Erasable programmable logic device
Device Family — Altera Classic EPLD Family
Speed Grade — 20 ns
Package Code — PC
Package Pin Count — [DATA_NEEDED: package pin count]
Package Dimensions — [DATA_NEEDED: package dimensions]
供應電壓 — [DATA_NEEDED: operating supply voltage]
I/O Count — [DATA_NEEDED: I/O count]
Internal Logic Capacity — 300 to 900 usable gates
Supported Logic Integration — Multiple PAL- and GAL-type devices
Programming Interface — [DATA_NEEDED: programming interface]
Programming Voltage — [DATA_NEEDED: programming voltage]
Mounting Technology — [DATA_NEEDED: mounting technology]
REACH Status — unknown
AEC-Q100 Qualification — not_applicable
Lead-Free Status — unknown
Halogen-Free Status — unknown

資料表與資源

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