EP610PC-30 vs EP610PC-35 比較
詳細並排比較 EP610PC-30 由 Altera 與 EP610PC-35 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610PC-30 | EP610PC-35 |
|---|---|---|
| 品牌 | Altera | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 啟用中 |
| Device Family | Classic EPLD (EP610) | — |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 30 ns | 37 ns (max, -35 speed grade) |
| Maximum Pipeline Frequency | 33.3 MHz (typical) / 100 MHz pipelined | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | CMOS EPROM | — |
| 封裝 | 24-pin PDIP (0.300 inch) | 24-pin PDIP (Plastic DIP, 0.600" wide, through-hole) |
| 安裝類型 | Through-Hole | Through Hole |
| Programmability | One-Time Programmable (OTP, no window on plastic PDIP) | — |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Output Drive Current | [DATA_NEEDED: IOH/IOL per datasheet DC characteristics] | — |
| Input Pins (Dedicated) | [DATA_NEEDED: dedicated input count from datasheet pinout] | — |
| I/O Pins | [DATA_NEEDED: bidirectional I/O count from datasheet pinout] | — |
| Programming Tool | Altera A+PLUS / MAX+PLUS II (legacy) | — |
| RoHS 狀態 | Not applicable (legacy non-compliant package per distributor listing) | [DATA_NEEDED: RoHS status - not confirmed in provided data] |
| Lead Free Status | Not applicable | — |
| Current Distributor | Rochester Electronics, LLC (authorized continuing source) | — |
| Device Type | — | EPLD (Erasable Programmable Logic Device) |
| Family | — | Classic EPLD |
| Internal Counter Frequency | — | up to 100 MHz |
| Supply Voltage - Internal | — | 4.75 V to 5.25 V |
| Programmable Type | — | EPLD (UV-erasable window variant: EP610DC; plastic OTP) |
| Supplier Device Package | — | 24-PDIP |
| Logic Family | — | CMOS |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |