EP610PC-35 vs EP610PC30 比較
詳細並排比較 EP610PC-35 由 Rochester Electronics 與 EP610PC30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610PC-35 | EP610PC30 |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | NRND |
| Device Type | EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | Classic EPLD | Classic EP610 |
| Macrocells | 16 | 16 |
| Usable Gates | 300 | 300 |
| Propagation Delay (tPD) | 37 ns (max, -35 speed grade) | 30 ns |
| Internal Counter Frequency | up to 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Supply Voltage - Internal | 4.75 V to 5.25 V | — |
| 工作溫度 | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Programmable Type | EPLD (UV-erasable window variant: EP610DC; plastic OTP) | — |
| 封裝 | 24-pin PDIP (Plastic DIP, 0.600" wide, through-hole) | PDIP-24 |
| 安裝類型 | Through Hole | Through-Hole |
| Supplier Device Package | 24-PDIP | — |
| Logic Family | CMOS | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - not confirmed in provided data] | Not applicable (legacy through-hole, contains Pb per historical datasheet) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Maximum Toggle Frequency | — | 33.3 MHz |
| Pipelined Data Rate | — | Up to 100 MHz |
| Technology | — | CMOS |
| Programming | — | EPROM/EEPROM-based, MAX+plus II toolchain |
| Logic Capacity | — | 16 macrocells / 300 gates equivalent |
| Configuration Memory | — | Non-volatile (UV-erasable or OTP variant) |
| Manufacturer (Original) | — | Altera Corporation (now Intel FPGA) |
| Current Distributor | — | Rochester Electronics, LLC |