EP610PI-30 vs EP610JI-30 比較
詳細並排比較 EP610PI-30 由 Rochester Electronics 與 EP610JI-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP610PI-30 | EP610JI-30 |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 最後購買 | NRND |
| Family | EP610 Classic EPLD | Altera Classic EPLD (EP610) |
| Logic Elements / Macrocells | 16 macrocells | — |
| Usable Gates | 300 gates | — |
| Propagation Delay (tPD) | 30 ns (PI-30 speed grade) | — |
| Maximum Frequency (pipelined) | 100 MHz | — |
| Process Technology | CMOS EEPROM | CMOS |
| Supply Voltage (VCC) | 5 V | — |
| 腳位數 | 24 | — |
| 封裝 | PDIP-24 (Plastic DIP) | CQCC28 (windowed ceramic JLCC, J-bend) |
| Number of Global Clocks | 2 | — |
| Number of Dedicated Inputs | 4 | — |
| Number of I/O Pins | 10 | — |
| Programming Technology | EEPROM (in-system, 100+ cycles) | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | -40C to +85C (industrial, per EP610 family suffix convention) |
| RoHS 狀態 | Not Compliant (per distributor data) | [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] |
| ECCN | EAR99 | — |
| HTS Code | 8542.39.00.01 | — |
| Device Type | — | UV Erasable Programmable Logic Device (EPLD) |
| Macrocells | — | 16 |
| Propagation Delay (tpd) | — | 30 ns (max) |
| Pipelined Data Rate | — | Up to 100 MHz |
| Product Terms | — | 160 |
| Dedicated Inputs | — | 4 |
| I/O Pins | — | 16 |
| External Clocks | — | 2 |
| 供應電壓 | — | 5 V (single supply) |
| Package Code | — | JLCC-28 / CQCC28 |
| Erasure Method | — | Ultraviolet (UV) via top window |
| Programming | — | Altera Logic Programmer compatible |
| 安裝類型 | — | Surface Mount (JLCC) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |