EP910DC-30 vs EP610DC-30 比較
詳細並排比較 EP910DC-30 由 Intel 與 EP610DC-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910DC-30 | EP610DC-30 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | Classic EPLD (EP910 series) | EP610 (Classic Device Family) |
| Architecture | PAL-type AND-OR sum-of-products, CMOS | — |
| Gate Count | 900 usable gates | — |
| Macrocells | 24 | 16 |
| Propagation Delay (tPD) | 30 ns (max) | 30 ns |
| Clock Frequency (fCNT) | 33.3 MHz | — |
| Dedicated Inputs | 36 | 16 |
| Outputs (Macrocells) | 24 | — |
| External Clock Pins | 2 (CLK1, CLK2) | — |
| 供應電壓 | 5 V | — |
| Process Technology | CMOS | — |
| Programming Method | UV-Erasable / OTP | — |
| 封裝 | DIP-40 (through-hole, 600 mil) | 24-pin CERDIP (windowed) |
| 工作溫度 | 0C to +70C (commercial) | Commercial (0C to +70C) |
| 安裝類型 | Through-Hole | Through-Hole |
| Product Type | — | Classic EPLD (Erasable Programmable Logic Device) |
| Logic Expanders | — | 4 (4 product terms per macrocell) |
| Usable Gates | — | 300 |
| Maximum Pipelined Clock Frequency | — | 100 MHz |
| I/O Pins | — | 16 (with output enable) |
| Speed Grade | — | -30 (30 ns tPD) |
| Technology | — | CMOS EPROM |
| Programmability | — | UV-erasable, windowed EPROM |
| Security Bit | — | Yes (protects design after programming) |
| Output Modes | — | Registered and Combinatorial |