EP910DI-35 vs EP910DI-30 比較

詳細並排比較 EP910DI-35 由 Altera 與 EP910DI-30 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP910DI-35 EP910DI-30
品牌 Altera Rochester Electronics
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 啟用中 NRND
Product Type EPLD (Erasable Programmable Logic Device) UV-Erasable Programmable Logic Device (EPLD)
Family Altera Classic EPLD Classic EPLD (Altera EP910 series)
Macrocells 24 —
Usable Gates 450 —
Propagation Delay (tPD) 35 ns —
Maximum Toggle Frequency (fCNT) 28.6 MHz —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (single supply)
Supply Current (ICC) 40 mA typical —
Dedicated Inputs 10 10
Bidirectional I/O Pins 20 —
Total Pins 40 —
封裝 CDIP-40 (Ceramic DIP with UV window) CDIP-40 (ceramic DIP, 40-pin with UV window)
安裝類型 Through-Hole Through-Hole (DIP)
工作溫度 -40C to +85C (industrial) -40C to +85C (industrial)
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable EPROM
Programming Method EPROM programmer + JEDEC fuse map —
Erasure Method UV light through quartz window —
RoHS 狀態 [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified] [DATA_NEEDED: RoHS compliance status]
Logic Family PAL-type AND/OR array with D flip-flops —
Manufacturer Original Altera; long-term authorized by Rochester Electronics, LLC —
Macrocell Count — 24
Propagation Delay (tpd) — 30 ns
Maximum Toggle Frequency (fmax) — 62 MHz
Dedicated I/O Pins — 12 (12 input + 12 output)
Output Enable Pins — 2
腳位數 — 40
Programmable Logic Element — JEDEC fuse map (3rd-party programmer)
Manufacturer (Original) — Altera (now Intel PSG)
Current Distributor / Authorized Aftermarket — Rochester Electronics, LLC

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