EP910IDI-15 vs EP910DI-30 比較

詳細並排比較 EP910IDI-15 由 Altera 與 EP910DI-30 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP910IDI-15 EP910DI-30
品牌 Altera Rochester Electronics
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete NRND
Family Classic EPLD Classic EPLD (Altera EP910 series)
Device Type CPLD (Complex Programmable Logic Device) —
Logic Gates 450 gates —
Macrocells 24 —
Maximum User I/O Pins 36 —
Pin-to-Pin Propagation Delay (tpd) 15 ns —
Maximum Counter Frequency 66.6 MHz —
Supply Voltage (Vcc) 5 V —
Technology CMOS EPROM CMOS, UV-erasable EPROM
Program/Erase Method UV-erasable windowed CerDIP —
封裝 40-pin CDIP (CerDIP) with quartz window CDIP-40 (ceramic DIP, 40-pin with UV window)
工作溫度 -40C to +85C (industrial, "I" grade) -40C to +85C (industrial)
安裝類型 Through-hole (DIP) Through-Hole (DIP)
Macrocells Configurable As D, T, JK, SR flip-flop, or combinatorial —
Development Tool MAX+PLUS II (legacy) / Altera Classic compiler —
Programming Hardware Altera Logic Programmer card —
RoHS 狀態 [DATA_NEEDED: RoHS compliance of CDIP windowed part] [DATA_NEEDED: RoHS compliance status]
Logic Family Compatibility Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages —
Product Type — UV-Erasable Programmable Logic Device (EPLD)
Macrocell Count — 24
Propagation Delay (tpd) — 30 ns
Maximum Toggle Frequency (fmax) — 62 MHz
Supply Voltage (VCC) — 5 V (single supply)
Dedicated Inputs — 10
Dedicated I/O Pins — 12 (12 input + 12 output)
Output Enable Pins — 2
腳位數 — 40
Programmable Logic Element — JEDEC fuse map (3rd-party programmer)
Manufacturer (Original) — Altera (now Intel PSG)
Current Distributor / Authorized Aftermarket — Rochester Electronics, LLC

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