EP910IDI-15 - 24-Macrocell Classic EPLD 15ns | Intel / Altera
MPN： EP910IDI-15 ✗ 停產EP910IDI-15 概覽
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that sits in the programmable-logic hierarchy between simple PAL/GAL devices and high-density FPGAs. The Classic EPLD family, introduced in the late 1980s and still in production via Rochester Electronics for legacy sustainment, is built on a CMOS EPROM-cell architecture and uses the MAX+PLUS II development environment for design entry, fitting, and programming. The EP910 sits in the lower-density end of the Classic family, intended for glue-logic, address decoding, state-machine, and bus-interface tasks that require deterministic 15-ns timing rather than the higher gate counts of FPGAs.
Key features include 24 individually programmable macrocells, each configurable as D, T, JK, or SR flip-flop or for combinatorial operation; 36 user I/O pins on the 40-pin CerDIP; a 15 ns pin-to-pin logic delay supporting counter frequencies up to approximately 66.6 MHz; and on-board logic-test circuitry that allows AC specification verification during production flow. The device is programmed using the Altera Logic Programmer card and the MAX+PLUS II software suite. All Classic EPLD members are pin-, function-, and programming-file compatible across speed grades and package variants, simplifying design migration.
Typical applications include address decoding and glue logic in legacy 5V microprocessor systems, bus-interface adapters for ISA/VME/Motorola bus architectures, replacement of multiple discrete PAL/GAL devices, industrial control state machines, and military/aerospace systems requiring ceramic-packaged, windowed reprogrammable logic for field updates. The CDIP-40 ceramic package with UV window supports field erasure and reprogramming, which is critical for long-life-cycle defense and aerospace sustainment programs.
When designing with the EP910IDI-15, note that this part operates from a single 5V supply and is fully static - there is no minimum clock frequency. Designers migrating from plastic DIP or PLCC EP910 variants (EP910PC-25, EP910LC-15, etc.) can drop in the same pinout but should account for the ceramic package's thermal characteristics if used in sealed or high-temperature environments.
直接替換替代品，適用於 EP910IDI-15 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EP910IDI-15 （相同外形與佔位） — 差異在於 Package, Family, Operating Temperature, Technology, Product Type.
EP910DC-15
✅ 直接替換聯絡詢價
查看資料表 →EP910DI-30
✅ 直接替換聯絡詢價
查看資料表 →EP910DI-35
✅ 直接替換聯絡詢價
查看資料表 →EP910DC-30
✅ 直接替換聯絡詢價
查看資料表 →EP910DC-35
✅ 直接替換聯絡詢價
查看資料表 →EP910DM-40
✅ 直接替換聯絡詢價
查看資料表 →DPLD910-15
✅ 直接替換📋 參考替代品（不在目錄中）
EP910IDI-15 最大額定值與電氣特性
| Family | Classic EPLD |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Logic Gates | 450 gates |
| Macrocells | 24 |
| Maximum User I/O Pins | 36 |
| Pin-to-Pin Propagation Delay (tpd) | 15 ns |
| Maximum Counter Frequency | 66.6 MHz |
| Supply Voltage (Vcc) | 5 V |
| Technology | CMOS EPROM |
| Program/Erase Method | UV-erasable windowed CerDIP |
| 封裝 | 40-pin CDIP (CerDIP) with quartz window |
| 工作溫度 | -40C to +85C (industrial, "I" grade) |
| 安裝類型 | Through-hole (DIP) |
| Macrocells Configurable As | D, T, JK, SR flip-flop, or combinatorial |
| Development Tool | MAX+PLUS II (legacy) / Altera Classic compiler |
| Programming Hardware | Altera Logic Programmer card |
| Logic Family Compatibility | Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages |
EP910IDI-15 腳位配置
| 腳位 1 | I/O — Bidirectional I/O pin (macrocell port) |
| 腳位 2 | I/O — Bidirectional I/O pin |
| 腳位 3 | I/O — Bidirectional I/O pin |
| 腳位 4 | I/O — Bidirectional I/O pin |
| 腳位 5 | I/O — Bidirectional I/O pin |
| 腳位 6 | I/O — Bidirectional I/O pin |
| 腳位 7 | I/O — Bidirectional I/O pin |
| 腳位 8 | I/O — Bidirectional I/O pin |
| 腳位 9 | I/O — Bidirectional I/O pin |
| 腳位 10 | I/O — Bidirectional I/O pin |
| 腳位 11 | I/O — Bidirectional I/O pin |
| 腳位 12 | I/O — Bidirectional I/O pin |
| 腳位 13 | IN1 — Dedicated global input (clock/control) |
| 腳位 14 | IN2 — Dedicated global input (clock/control) |
| 腳位 15 | IN3 — Dedicated global input (clock/control) |
| 腳位 16 | IN4 — Dedicated global input (clock/control) |
| 腳位 17 | I/O — Bidirectional I/O pin |
| 腳位 18 | I/O — Bidirectional I/O pin |
| 腳位 19 | I/O — Bidirectional I/O pin |
| 腳位 20 | GND — Ground |
| 腳位 21 | I/O — Bidirectional I/O pin |
| 腳位 22 | I/O — Bidirectional I/O pin |
| 腳位 23 | I/O — Bidirectional I/O pin |
| 腳位 24 | I/O — Bidirectional I/O pin |
| 腳位 25 | I/O — Bidirectional I/O pin |
| 腳位 26 | I/O — Bidirectional I/O pin |
| 腳位 27 | I/O — Bidirectional I/O pin |
| 腳位 28 | I/O — Bidirectional I/O pin |
| 腳位 29 | I/O — Bidirectional I/O pin |
| 腳位 30 | I/O — Bidirectional I/O pin |
| 腳位 31 | I/O — Bidirectional I/O pin |
| 腳位 32 | I/O — Bidirectional I/O pin |
| 腳位 33 | OUT1 — Dedicated global output (high-speed) |
| 腳位 34 | OUT2 — Dedicated global output (high-speed) |
| 腳位 35 | OUT3 — Dedicated global output (high-speed) |
| 腳位 36 | OUT4 — Dedicated global output (high-speed) |
| 腳位 37 | I/O — Bidirectional I/O pin |
| 腳位 38 | I/O — Bidirectional I/O pin |
| 腳位 39 | I/O — Bidirectional I/O pin |
| 腳位 40 | VCC — +5V supply |
典型應用
EP910IDI-15 適用於 6 應用s: 5V Address Decoding Glue Logic, Industrial Control State Machines, Legacy Bus Interface Adapters, PAL/GAL Replacement and Consolidation, Military and Aerospace Sustainment Systems, Prototype and Educational Logic Development.
5V Address Decoding Glue Logic
The EP910IDI-15's 24 macrocells and 36 I/O pins are well matched to 5V microprocessor address-decoding tasks in ISA, VME, and Motorola 68000 bus architectures. Its 15 ns pin-to-pin tpd places the part comfortably within the address-to-chip-select decode window of 8- and 16-bit microprocessors running up to ~25 MHz. Compared to discrete 74LS/74F TTL decoder logic, the EP910IDI-15 replaces multiple packages with a single reprogrammable device, simplifying PCB layout and enabling late-stage design changes via UV erasure.
推薦
Industrial Control State Machines
The EP910IDI-15's 24 macrocells are sufficient for medium-complexity state machines (8-16 states with multiple outputs) commonly found in industrial controllers, PLC I/O modules, and process-control subsystems. Each macrocell is configurable as D, T, JK, or SR flip-flop, giving designers full flexibility for sequential logic. The industrial -40C to +85C operating temperature and ceramic CDIP-40 package suit sealed enclosures and factory-floor environments; the UV window enables field firmware updates without board replacement.
推薦
Legacy Bus Interface Adapters
The EP910IDI-15's 15 ns tpd and 66.6 MHz max counter frequency support bus-interface adaptation for legacy parallel buses such as ISA, VMEbus, PC/104, and Multibus. The 36 I/O pins accommodate 16-bit data paths plus control and address signals within a single device, replacing 3-5 discrete TTL packages. The ceramic CDIP-40 with UV window allows field reconfiguration when bus standards evolve, which is critical for defense and aerospace sustainment programs where the bus architecture is fixed but the peripheral set changes over decades.
推薦
PAL/GAL Replacement and Consolidation
The EP910IDI-15 is a drop-in consolidation target for designs that previously used two to four 20- or 24-pin PAL/GAL devices. With 24 macrocells and 36 I/O, a single EP910IDI-15 absorbs the logic of multiple legacy programmable devices while preserving the 5V CMOS EPROM programming model familiar to PAL/GAL designers. The MAX+PLUS II toolchain accepts standard CUPL/ABEL-style equations, easing migration. The UV-erasable window is invaluable during development cycles, allowing rapid design iteration without package discard.
推薦
Military and Aerospace Sustainment Systems
The EP910IDI-15 is widely deployed in legacy defense and aerospace systems where its ceramic CDIP-40 windowed package, -40C to +85C industrial operating range, and Intel / Altera Classic EPLD architecture support long sustainment cycles. Rochester Electronics manufactures the part under the original Altera datasheet for ongoing defense logistics support. Its 15 ns tpd supports avionics bus timing, weapon-system interface logic, and legacy radar-signal routing where modern surface-mount CPLDs are not acceptable substitutes.
推薦
Prototype and Educational Logic Development
The EP910IDI-15's UV-erasable window, 5V single supply, and through-hole CDIP-40 footprint make it well suited to university digital-logic laboratories and engineering prototypes where students can erase and reprogram the device repeatedly. The 24 macrocells provide enough capacity for full single-cycle MIPS datapath sections, UART cores, or complete FSM-based controllers without exceeding the device. The MAX+PLUS II student-edition toolchain (legacy) supports schematic and AHDL entry, simplifying the teaching workflow.
推薦
推薦產品摘要
工程參考資料，適用於 EP910IDI-15 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EP910DC-15 | EP910DI-30 | EP910DI-35 | EP910DM-40 | DPLD910-15 |
|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | ICT |
| Package | 40-pin CDIP windowed | 40-pin PDIP (plastic, same footprint) | 40-pin CDIP windowed (same) | 40-pin CDIP windowed (same) | 40-pin CDIP windowed (same) | 40-pin WDIP windowed (same footprint) |
| Pin-to-Pin tpd | 15 ns | 15 ns (identical) | 30 ns (slower) | 35 ns (slower) | 40 ns (slower) | 15 ns (identical) |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Gates | 450 | 450 | 450 | 450 | 450 | 450 |
| User I/O | 36 | 36 | 36 | 36 | 36 | 36 |
| UV-Erasable Window | Yes | No (plastic DIP, OTP) | Yes | Yes | Yes | Yes |
| Lifecycle Status | Obsolete (Rochester sustainment) | Obsolete (Rochester sustainment) | Obsolete (Rochester sustainment) | Obsolete (Rochester sustainment) | Obsolete (Rochester sustainment) | Obsolete |
主要差異化特點
- UV-erasable windowed ceramic CDIP-40 package (對比EP910DC-15)
- 15 ns pin-to-pin delay - fastest speed grade in CDIP-40 (對比EP910DI-30)
- Industrial -40C to +85C operating range with ceramic reliability (對比DPLD910-15)
設計說明
When substituting the EP910IDI-15 with EP910DC-15 (plastic DIP) or with slower EP910DI-30 / EP910DI-35, verify that the slower propagation delay still meets the system's address-to-chip-select timing budget. A 30 ns part is roughly half the speed of the 15 ns grade; in 25 MHz 68000 systems with tight decode windows, this can cause intermittent address-decode failures that are notoriously hard to debug.
The 40-pin CDIP-40 CerDIP socket should be a high-quality machined-pin or dual-leaf socket with gold or tin plating rated for repeated insertion cycles. UV-erasable EP910IDI-15 parts are routinely removed for erasure and reprogramming during development; lower-grade sockets will develop high-resistance contacts after 20-50 insertion cycles, causing intermittent programming failures.
Estimated: at 5V Vcc and a typical 24-macrocell utilization switching at 10 MHz with 50% toggle rate, the EP910IDI-15 draws approximately 60-90 mA from Vcc. Decoupling with a 0.1 uF ceramic cap directly across pins 20 (GND) and 40 (VCC), plus a 10 uF tantalum bulk cap within 1 inch of the package, is required to suppress switching-noise injection into adjacent analog or memory sections.
Keep the EP910IDI-15 away from high-current switching regulators or motor-driver traces; its CMOS EPROM cells can retain programmed state for decades, but marginal data retention has been reported when devices are operated continuously near maximum Vcc with elevated ambient temperature. The CDIP-40 ceramic package has higher thermal mass than the plastic PDIP, which helps in sealed enclosures.
合規資訊
The EP910IDI-15 is a legacy Classic EPLD originally designed before RoHS took effect. RoHS/REACH compliance for the windowed CDIP-40 variant is not explicitly stated in indexed search results and is flagged [DATA_NEEDED]. For defense/aerospace sustainment, parts from Rochester Electronics carry original Altera datasheet traceability; commercial RoHS compliance may require specific date codes. AEC-Q100 is not applicable as this is a programmable logic device, not an automotive-grade IC.
