EP910IDI-15 vs EP910DI-35 比較

詳細並排比較 EP910IDI-15 由 Altera 與 EP910DI-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP910IDI-15 EP910DI-35
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Obsolete 啟用中
Family Classic EPLD Altera Classic EPLD
Device Type CPLD (Complex Programmable Logic Device) —
Logic Gates 450 gates —
Macrocells 24 24
Maximum User I/O Pins 36 —
Pin-to-Pin Propagation Delay (tpd) 15 ns —
Maximum Counter Frequency 66.6 MHz —
Supply Voltage (Vcc) 5 V —
Technology CMOS EPROM CMOS, UV-erasable EPROM
Program/Erase Method UV-erasable windowed CerDIP —
封裝 40-pin CDIP (CerDIP) with quartz window CDIP-40 (Ceramic DIP with UV window)
工作溫度 -40C to +85C (industrial, "I" grade) -40C to +85C (industrial)
安裝類型 Through-hole (DIP) Through-Hole
Macrocells Configurable As D, T, JK, SR flip-flop, or combinatorial —
Development Tool MAX+PLUS II (legacy) / Altera Classic compiler —
Programming Hardware Altera Logic Programmer card —
RoHS 狀態 [DATA_NEEDED: RoHS compliance of CDIP windowed part] [DATA_NEEDED: RoHS status - ceramic CDIP legacy parts are typically non-compliant unless specified]
Logic Family Compatibility Pin-, function-, and JEDEC-map compatible across all EP910 speed grades and packages —
Product Type — EPLD (Erasable Programmable Logic Device)
Usable Gates — 450
Propagation Delay (tPD) — 35 ns
Maximum Toggle Frequency (fCNT) — 28.6 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V (5 V nominal)
Supply Current (ICC) — 40 mA typical
Dedicated Inputs — 10
Bidirectional I/O Pins — 20
Total Pins — 40
Programming Method — EPROM programmer + JEDEC fuse map
Erasure Method — UV light through quartz window
Logic Family — PAL-type AND/OR array with D flip-flops
Manufacturer — Original Altera; long-term authorized by Rochester Electronics, LLC

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