EP910ILC-15 vs EP910ILC-15N 比較
詳細並排比較 EP910ILC-15 由 Intel 與 EP910ILC-15N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N Obsolete規格比較
| 參數 | EP910ILC-15 | EP910ILC-15N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Classic EPLD | Classic |
| Series | EP910 | — |
| Logic Gates | 450 | 450 |
| Macrocells | 24 | — |
| User I/O Pins | 36 | 36 |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 83.33 MHz | 66.6 MHz |
| 供應電壓 | 5 V | — |
| 記憶體類型 | EPROM (UV-erasable) | — |
| 工作溫度 | -40C to +85C (industrial) | 0 C to +70 C (commercial) |
| 封裝 | 44-pin PLCC (J-lead) | PLCC-44 (J-lead, surface mount) |
| 安裝類型 | Surface Mount (SMT) | Surface Mount |
| Propagation Class | -15 speed grade | — |
| Storage Condition | Dry cabinet, humidity-controlled | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | Compliant |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Dedicated Input Pins | — | 16 |
| Process Technology | — | CMOS EPROM (one-time programmable) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Programming | — | EPROM / JTAG (Classic EP-series) |