EP910ILC-50 vs EP910IPC-50 比較
詳細並排比較 EP910ILC-50 由 Intel 與 EP910IPC-50 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910ILC-50 | EP910IPC-50 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | — |
| Usable Gates | 900 (typical) | — |
| Maximum Frequency | [DATA_NEEDED: fMAX value from datasheet] | — |
| Pin-to-Pin Delay (tpd) | 50 ns | — |
| Supply Voltage (VCC) | 5 V (typical) | 4.75 V to 5.25 V (5 V nominal) |
| User I/O Pins | 24 | 24 |
| Dedicated Input Pins | 12 | — |
| 封裝 | PLCC-44 (J-lead) | 40-pin Ceramic DIP (IPC, windowed) |
| 安裝類型 | Surface Mount (socket-compatible) | Through-Hole (DIP) |
| Technology | CMOS EPROM, UV-erasable | CMOS EPROM cell |
| 工作溫度 | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Programming Cycles | 100 (minimum) | — |
| Boundary Scan | IEEE 1149.1 JTAG (selected speed grades) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: not stated in verified data] |
| Product Type | — | Erasable Programmable Logic Device (EPLD) |
| Logic Capacity | — | [DATA_NEEDED: macrocell count / equivalent gates] |
| Propagation Delay (tPD) | — | 50 ns |
| Clock-to-Output (tCO) | — | 35 ns |
| Maximum Toggle Frequency | — | [DATA_NEEDED: fMAX] |
| Programming Method | — | Off-board EPROM programmer + UV erase |
| Erasure Method | — | UV light through ceramic window (IPC package) |