EP910IPC-12 vs EP910LI-20 比較
詳細並排比較 EP910IPC-12 由 Altera 與 EP910LI-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910IPC-12 | EP910LI-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Maximum Operating Frequency (fMAX) | 76.9 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 12 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Dedicated Inputs | 10 | 16 |
| I/O Pins | 24 | 24 |
| 封裝 | 40-pin PDIP | 40-pin Ceramic DIP (Windowed) |
| 安裝類型 | Through Hole | — |
| Technology | CMOS EPLD (UV-erasable or OTP) | CMOS, UV-erasable |
| 工作溫度 | -40C to +85C (industrial) | -40C to +85C (Industrial) |
| Programming Toolchain | MAX+PLUS II | — |
| Logic Capacity | Equivalent to ~24 PAL16V8s | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Maximum Operating Frequency | — | 62 MHz |
| Propagation Delay (tpd) | — | 20 ns |
| Package Type | — | Through-Hole, Ceramic DIP with Quartz Window |
| Temperature Grade | — | Industrial (-40C to +85C) |
| 腳位數 | — | 40 |
| Logic Family | — | EPLD (Erasable PLD) |
| Architecture | — | Sum-of-products macrocell |
| Pin/Package Compatibility | — | Pin-compatible across EP910 family |