EP910IPC-15 vs EP910DC-15 比較
詳細並排比較 EP910IPC-15 由 Altera 與 EP910DC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910IPC-15 | EP910DC-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD (EP910 series) | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Architecture | PAL-type, CMOS | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | — |
| Product Terms | 240 | — |
| External Clocks | 2 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V (typical) |
| 工作溫度 | 0C to +70C (commercial, IPC suffix) | 0C to +70C (commercial) |
| 封裝 | PDIP-40 (Plastic DIP, 40-pin) | 24-pin ceramic DIP (DC) |
| 安裝類型 | Through-Hole | Through-Hole |
| Process Technology | CMOS | — |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | — |
| 腳位數 | 40 | — |
| RoHS 狀態 | [DATA_NEEDED: rohs status not confirmed in verified data] | [DATA_NEEDED: not explicitly stated in verified data] |
| Family | — | Altera Classic EPLD |
| Device Density | — | 900 usable gates |
| Logic Elements | — | [DATA_NEEDED: exact LE count] |
| Bidirectional I/O Pins | — | 12 |
| Flip-Flops | — | 10 |
| Product Terms per Macrocells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Speed Grade | — | 15 |
| Technology | — | CMOS EPROM, UV-erasable |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |