EP910IPC-15 - Altera Classic EPLD 24-Macrocell 15ns DIP-40
MPN： EP910IPC-15 ✗ 停產EP910IPC-15 概覽
A Classic EPLD is a CMOS-based programmable logic device that combines the integration density of a small PLD with the simple, non-volatile architecture of a PAL. The EP910 sits in the hierarchy of programmable logic between simple SPLDs (PAL/GAL, tens of gates) and complex PLDs/early CPLDs (hundreds of macrocells), and is fabricated on an advanced CMOS process that gives it the low-power, high-noise-immunity characteristics engineers expect from CMOS PAL replacements. The "Classic" label distinguishes this family from later MAX-series CPLDs that added in-system programmability and higher macrocell counts.
Key features include a 15 ns worst-case combinatorial propagation delay (tPD), 24 macrocells with 240 product terms for sum-of-products logic, two global clock networks for registered logic, and a typical standby current in the milliamp range on a 5 V rail. Programming is performed via a standard Altera EPLD programmer using a JEDEC fuse map, and the device is erasable in a UV chamber (windowed CERDIP versions exist in the family), making it suitable for prototyping before committing to one-time-programmable (OTP) plastic DIP.
Architecture-wise, the EP910 uses a PAL-type AND-OR structure with a global interconnect: each macrocell owns a fixed fan-in product term group that feeds an OR array, then a configurable output cell that can be registered or combinatorial. The "IPC" suffix denotes the industrial temperature grade with a ceramic/plastic 40-pin DIP package, and the "-15" speed grade places it in the mid-speed bin of the EP910 series alongside the -25 and -35 variants.
Typical applications include board-level glue logic replacement, state-machine decoding, address decoding in microprocessor systems, peripheral interface adapters, and bus-arbitration controllers in industrial control and instrumentation equipment. The DIP-40 footprint is favored in legacy through-hole designs and breadboard prototyping.
When designing with the EP910IPC-15, ensure the supply rail stays within 4.75 V to 5.25 V and respect the 15 ns timing budget across temperature. Unused I/O pins should be left floating or tied to a defined logic level per the Altera EPLD design guidelines to minimize quiescent current draw.
This page synthesizes distributor stock, pricing, and drop-in alternatives not consolidated on the original Altera datasheet, enabling faster sourcing and second-source decisions for the EP910 Classic EPLD family.
直接替換替代品，適用於 EP910IPC-15 — 相同封裝，腳位對腳位相容。需重新設計 PCB 的不同封裝零件不列入。
此系列的變體
與下列產品可直接替換的同系列型號： EP910IPC-15 （相同外形與佔位） — 差異在於 Package, Technology, Programming Method, Family, Operating Temperature.
EP910IDC-15
✅ 直接替換聯絡詢價
查看資料表 →EP910DC-15
✅ 直接替換聯絡詢價
查看資料表 →EP910ILC-15
✅ 直接替換 ⚠️ 規格未經驗證聯絡詢價
查看資料表 →EP910DC-30
✅ 直接替換聯絡詢價
查看資料表 →EP910DC-35
✅ 直接替換聯絡詢價
查看資料表 →DPLD910-12
✅ 直接替換📋 參考替代品（不在目錄中）
EP910IPC-15 最大額定值與電氣特性
| Device Family | Altera Classic EPLD (EP910 series) |
| Product Type | Erasable Programmable Logic Device (EPLD) |
| Architecture | PAL-type, CMOS |
| Macrocells | 24 |
| Dedicated Inputs | 12 |
| I/O Pins | 24 |
| Product Terms | 240 |
| External Clocks | 2 |
| Propagation Delay (tPD) | 15 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V |
| 工作溫度 | 0C to +70C (commercial, IPC suffix) |
| 封裝 | PDIP-40 (Plastic DIP, 40-pin) |
| 安裝類型 | Through-Hole |
| Process Technology | CMOS |
| Programming Method | JEDEC fuse map via Altera EPLD programmer |
| 腳位數 | 40 |
EP910IPC-15 腳位配置
| 腳位 1 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 2 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 3 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 4 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 5 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 6 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 7 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 8 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 9 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 10 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 11 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 12 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 13 | INPUT — Dedicated input pin |
| 腳位 14 | INPUT — Dedicated input pin |
| 腳位 15 | INPUT — Dedicated input pin |
| 腳位 16 | INPUT — Dedicated input pin |
| 腳位 17 | INPUT — Dedicated input pin |
| 腳位 18 | INPUT — Dedicated input pin |
| 腳位 19 | INPUT — Dedicated input pin |
| 腳位 20 | VCC — 5 V supply voltage (4.75 V to 5.25 V) |
| 腳位 21 | INPUT — Dedicated input pin |
| 腳位 22 | INPUT — Dedicated input pin |
| 腳位 23 | INPUT — Dedicated input pin |
| 腳位 24 | INPUT — Dedicated input pin |
| 腳位 25 | INPUT — Dedicated input pin |
| 腳位 26 | INPUT — Dedicated input pin |
| 腳位 27 | CLK0 — Global clock input 0 |
| 腳位 28 | CLK1 — Global clock input 1 |
| 腳位 29 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 30 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 31 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 32 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 33 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 34 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 35 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 36 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 37 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 38 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 39 | I/O — Bidirectional I/O pin (macrocell-driven) |
| 腳位 40 | GND — Ground reference |
典型應用
EP910IPC-15 適用於 6 應用s: Microprocessor Address Decoding, State Machine Controllers, Bus Arbitration Logic, Peripheral Interface Adapters, Glue Logic Replacement for TTL/CMOS, Industrial Control Logic.
Microprocessor Address Decoding
The EP910IPC-15 is well-suited to microprocessor address decoding in 8-bit and 16-bit embedded systems because its 24 macrocells provide ample capacity for complex memory-mapped chip-select logic while the 15 ns tPD comfortably meets the address-to-chip-select timing requirement of 8086, 68000, and Z80 buses at moderate clock speeds. With 24 I/O pins it can decode multiple peripherals or memory banks simultaneously. Its 5 V-only CMOS I/O matches the logic levels of legacy microprocessors and TTL peripherals directly, eliminating level shifters. The PDIP-40 footprint is also ideal for legacy through-hole CPU boards where SMD CPLDs are impractical.
推薦
State Machine Controllers
The EP910IPC-15's 24 macrocells and 240 product terms deliver enough logic capacity to implement medium-complexity FSMs (10-20 states) typical of industrial controller sequencers, while its 2 global clock networks support registered outputs with predictable clock-to-out timing. The 15 ns tPD provides comfortable setup margin for state decoding at clock rates up to about 30 MHz. The CMOS PAL-type AND-OR structure maps naturally to sum-of-products state-transition logic, and the JEDEC fuse-map programming flow lets engineers iterate quickly on legacy programmer hardware. For harsh-environment versions use the EP910IDC-15, otherwise the EP910IPC-15 is the standard commercial choice.
推薦
Bus Arbitration Logic
Bus arbiters in multi-master systems benefit from the EP910IPC-15's combination of 15 ns propagation delay - which keeps arbitration decision time short relative to typical bus cycles - and 24 I/O pins that accommodate the request/grant signals of 4 to 8 master ports. The 240 product terms are sufficient to encode priority encoders and grant-mask logic for VME, Multibus, or proprietary backplanes. Its 5 V CMOS outputs drive TTL peripherals directly, and the PAL-type AND-OR array expresses arbitration equations efficiently. Use the EP910IPC-15 in commercial systems, or step up to EP910IDC-15 for industrial-grade multi-master backplanes.
推薦
Peripheral Interface Adapters
The EP910IPC-15 is a flexible peripheral interface adapter because its 24 macrocells can implement custom parallel-port, GPIB-like, or proprietary bus protocols, while 12 dedicated inputs simplify clock/handshake capture. The 15 ns tPD ensures compliant timing for legacy peripheral buses such as SCSI, IEEE-488, or Centronics-extensions without buffering. CMOS 5 V I/O is directly compatible with TTL peripherals, and the 40-pin PDIP simplifies through-hole backplane designs. The part is also widely available as NOS inventory, making it a practical choice for maintaining legacy test equipment.
推薦
Glue Logic Replacement for TTL/CMOS
The EP910IPC-15 replaces dozens of 74LS/74HC discrete glue-logic packages - such as address latches, parity generators, and custom encoders - with a single programmable device, dramatically reducing board area and improving reliability through fewer solder joints. Its 24 macrocells at 15 ns tPD consolidate what would otherwise be 8-15 standard-logic packages. The CMOS process gives it a quiescent current in the milliamp range versus the cumulative draw of equivalent discrete TTL gates. Designers should follow Altera's EPLD design guidelines and tie unused I/Os to a defined logic level.
推薦
Industrial Control Logic
The EP910IPC-15 serves as the central logic block in industrial control PLCs, machine controllers, and instrumentation front-ends where its 24 macrocells encode ladder-logic-equivalent Boolean equations, sequencer tables, and alarm-processing logic. The 15 ns propagation delay handles encoder-decoder interfaces and interrupt-priority logic at typical control-loop update rates, while the 5 V CMOS I/O interfaces directly with optocouplers and 24 V-level translators commonly used in factory environments. The PDIP-40 package suits through-hole backplanes preferred in legacy industrial designs. For harsher temperatures use EP910IDC-15 instead.
推薦
推薦產品摘要
工程參考資料，適用於 EP910IPC-15 — 比較、設計指引及合規資訊。
選型指南
與替代品比較
| 參數 | 本產品 | EP910IDC-15 | EP910DC-15 | EP910ILC-15 | EP910DC-30 | DPLD910-12 |
|---|---|---|---|---|---|---|
| Package | PDIP-40 (Plastic DIP) | DIP-40 (CERDIP) | DIP-40 (CERDIP, windowed) | PLCC-44 - NOT pin-compatible | DIP-40 (CERDIP) | DIP-40 |
| Brand | Altera (Intel FPGA) | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 24 | 24 | 24 | 24 | 24 | 24 |
| Propagation Delay (tPD) | 15 ns | 15 ns | 15 ns | 15 ns | 30 ns | 12 ns |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) | 0C to +70C (commercial CERDIP) | 0C to +70C (commercial PLCC) | 0C to +70C | 0C to +70C |
| I/O Pins | 24 | 24 | 24 | 24 | 24 | 24 |
| Product Terms | 240 | 240 | 240 | 240 | 240 | 240 |
| Lifecycle Status | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) | Obsolete (EOL) |
主要差異化特點
- Industrial-temperature CERDIP drop-in upgrade (對比EP910IPC-15)
- Windowed CERDIP for iterative prototyping (對比EP910IPC-15)
- Faster speed grade available (對比DPLD910-12)
設計說明
The EP910IPC-15 operates from a single 5 V supply with a permitted range of 4.75 V to 5.25 V. Decouple VCC (pin 20) with a 0.1 uF ceramic capacitor placed as close to the package as possible, plus a bulk 10 uF tantalum or aluminum electrolytic on the supply rail. The device draws CMOS-class quiescent current but additional dynamic current scales with output switching frequency and load capacitance - budget the regulator for at least 100 mA per EP910IPC-15 plus I/O loading. Do not operate below 4.75 V as logic levels and propagation delay are only guaranteed within the specified range.
Do not connect the EP910IPC-15 to 3.3 V logic signals directly - the device's input and I/O pins are 5 V CMOS and may be damaged by voltages exceeding VCC. Add level shifters (e.g., 74HCT245 or modern logic translators) when interfacing to 3.3 V microcontrollers. Unused I/O pins should be configured as outputs driving a defined logic level, or left floating per the Altera EPLD design guidelines. Verify the JEDEC fuse map against the Altera programming software to avoid pin conflicts between dedicated inputs and bidirectional I/Os.
For through-hole PDIP-40 designs, route VCC and GND on a power plane or wide traces to minimize switching noise. Keep clock traces (CLK0/CLK1) short and away from high-current output switching to avoid ground bounce coupling into the clock inputs. Place decoupling capacitors within 5 mm of the VCC pin. For noisy environments, add a small ferrite bead or 10 ohm resistor in series with VCC near the device to filter supply transients. The 40-pin DIP package is forgiving of layout but still benefits from a ground pour on the component side.
合規資訊
EP910IPC-15 is a legacy Altera Classic EPLD; RoHS/REACH/lead-free status not confirmed in verified web data. The part was originally specified before RoHS directives took effect, so lead-free status should be verified on a per-lot basis via the actual distributor documentation. AEC-Q100 is not applicable - this is a CMOS PLD, not an automotive-qualified IC.
