EP910IPC-15 vs EP910PC-25 比較
詳細並排比較 EP910IPC-15 由 Altera 與 EP910PC-25 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910IPC-15 | EP910PC-25 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD (EP910 series) | — |
| Product Type | Erasable Programmable Logic Device (EPLD) | — |
| Architecture | PAL-type, CMOS | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 10 |
| I/O Pins | 24 | — |
| Product Terms | 240 | — |
| External Clocks | 2 | — |
| Propagation Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 5 V +/- 10% |
| 工作溫度 | 0C to +70C (commercial, IPC suffix) | 0C to +70C (commercial) |
| 封裝 | PDIP-40 (Plastic DIP, 40-pin) | PDIP-24 (Plastic DIP) |
| 安裝類型 | Through-Hole | — |
| Process Technology | CMOS | — |
| Programming Method | JEDEC fuse map via Altera EPLD programmer | — |
| 腳位數 | 40 | 24 |
| RoHS 狀態 | [DATA_NEEDED: rohs status not confirmed in verified data] | — |
| Product Family | — | Classic EPLD |
| Usable Gates | — | 900 |
| Integration Gates (typical) | — | 4800 |
| Pin-to-Pin Delay (tPD) | — | 25 ns |
| Maximum Operating Frequency (fMAX) | — | 33.3 MHz |
| Technology | — | CMOS EPROM |
| Dedicated I/O Pins | — | 12 |
| TTL Compatibility | — | 100% TTL emulation |
| Erasure Method | — | Not erasable in plastic package (windowless) |