EP910JC-30 vs EP910LC-40 比較
詳細並排比較 EP910JC-30 由 Intel 與 EP910LC-40 由 Rochester Electronics. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP910LC-40 - 450-Gate CMOS EPLD, 40ns, PQCC-44 | Rochester / Altera
EP910LC-40 Obsolete規格比較
| 參數 | EP910JC-30 | EP910LC-40 |
|---|---|---|
| 品牌 | Intel | Rochester Electronics |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Classic EPLD (MAX-style) | — |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Internal Frequency (Fmax) | 33.3 MHz | — |
| Macrocells | 24 | 24 |
| Inputs | 36 | — |
| Product Terms | 240 | — |
| Outputs | 10 dedicated | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | CMOS EPROM, UV-erasable | CMOS EPROM |
| 封裝 | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) | PQCC-44 (Plastic Leaded Chip Carrier, J-lead) |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | — |
| Supply Current (Icc) | [DATA_NEEDED: Icc typical / maximum] | — |
| 安裝類型 | Surface Mount (socket-mountable) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | Not applicable (legacy) |
| Logic Blocks | 24 macrocells (AND/OR array architecture) | — |
| Manufacturer | — | Rochester Electronics (Altera original) |
| Device Family | — | Altera Classic EPLD - EP910 |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 450 |
| Logic Array Blocks | — | 2 (12 macrocells each) |
| Propagation Delay (tPD) | — | 40 ns |
| Maximum Toggle Frequency (fMAX) | — | 25 MHz |
| User I/O Pins | — | 36 |
| Dedicated Inputs | — | 4 |
| Supply Voltage (VCC) | — | 5 V (single supply) |
| Operating Temperature (Commercial) | — | 0 C to +70 C |
| Programming Method | — | Altera Logic Programmer (PLAD-J), 4-wire serial |
| Lead-Free Status | — | Not applicable |