EP910LC-35T vs EP910LC-32 比較
詳細並排比較 EP910LC-35T 由 Altera 與 EP910LC-32 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LC-35T | EP910LC-32 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | Obsolete |
| Family | Classic EPLD (EP910) | — |
| Logic Capacity | 450 usable gates | — |
| Macrocells | 24 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Operating Frequency | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V |
| User I/O Pins | 36 | — |
| 封裝 | PLCC-44 (J-lead) | PLCC-32 |
| Process Technology | CMOS (EPROM-based) | — |
| 工作溫度 | 0C to +70C (commercial) | — |
| Erasure Method | UV-erasable window (ceramic package) / OTP (plastic) | — |
| Programming | Altera programming hardware + MAX+PLUS II | — |
| 安裝類型 | Surface Mount (PLCC socket or solder) | Surface Mount (PLCC socket or direct solder) |
| MSL 等級 | MSL 3 (168 hours) | unknown |
| RoHS 狀態 | [DATA_NEEDED: RoHS status not in verified data] | unknown |
| Device Family | — | Altera Classic EPLD |
| Number of Macrocells | — | 24 |
| Number of Usable Gates | — | 900 gates (typical) |
| Number of Dedicated Inputs | — | 10 |
| Number of I/O Pins | — | 20 |
| Speed Grade | — | -32 |
| Maximum Toggle Frequency (fMAX) | — | [DATA_NEEDED: fMAX value in MHz for -32 grade] |
| Pin-to-Pin Propagation Delay (tPD) | — | [DATA_NEEDED: tPD in ns for -32 grade] |
| Logic Family | — | Low-power CMOS (LC suffix) |
| Programming Method | — | UV-erasable or one-time programmable (OTP for LC windowless variant) |
| 工作溫度範圍 | — | [DATA_NEEDED: commercial or industrial grade] |
| I/O Standard | — | TTL-compatible |