EP910LI-30 vs EP910LC-30 比較
詳細並排比較 EP910LI-30 由 Rochester Electronics 與 EP910LC-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP910LI-30 - 24-Macrocell EPLD, 30ns, PQCC44 | Rochester/Altera
EP910LI-30 Obsolete
規格比較
| 參數 | EP910LI-30 | EP910LC-30 |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD EP910 | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 24 | — |
| Equivalent Gates | 450 | — |
| Propagation Delay (tPD) | 30 ns | 30 ns (max) |
| Supply Voltage (VCC) | 5 V ±5% (4.75 V to 5.25 V) | 5 V (nominal, TTL) |
| Supply Current (ICC) | [DATA_NEEDED: ICC standby/active] | — |
| 工作溫度 | -40C to +85C (Industrial) | — |
| Process Technology | CMOS EPROM, UV-erasable | CMOS (EPROM-based) |
| 封裝 | 44-pin PQCC / PLCC-44 (J-lead) | — |
| 安裝類型 | Surface Mount (socket recommended for UV erasure) | — |
| Dedicated Inputs | 10 | — |
| I/O Pins | 22 | — |
| Programming Method | Altera EPLD programming algorithm / MAX+PLUS II legacy support | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance not verified in scraped data] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Manufacturer (Original) | Altera (now Intel PSG) | — |
| Current Stocking Channel | Rochester Electronics (authorized aftermarket) | — |
| Macrocell Count | — | 24 |
| Maximum Toggle Frequency | — | 62 MHz |
| Package Type | — | PDIP-40 (Plastic DIP, through-hole) |
| Operating Temperature Grade | — | Commercial (0C to +70C) |
| I/O Pin Count | — | 24 |
| Dedicated Input Pins | — | 36 (including I/O) |
| Product Terms per Macrocell | — | Up to 16 |
| Programming Technology | — | UV-erasable EPROM cell |
| Development Tool | — | Altera MAX+PLUS II |
| MSL 等級 | — | [DATA_NEEDED: MSL level] |