EP910LI-30 vs EP910LI-35BF 比較
詳細並排比較 EP910LI-30 由 Rochester Electronics 與 EP910LI-35BF 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP910LI-30 - 24-Macrocell EPLD, 30ns, PQCC44 | Rochester/Altera
EP910LI-30 Obsolete規格比較
| 參數 | EP910LI-30 | EP910LI-35BF |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD EP910 | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 24 | 24 |
| Equivalent Gates | 450 | — |
| Propagation Delay (tPD) | 30 ns | — |
| Supply Voltage (VCC) | 5 V ±5% (4.75 V to 5.25 V) | 5 V (nominal) |
| Supply Current (ICC) | [DATA_NEEDED: ICC standby/active] | — |
| 工作溫度 | -40C to +85C (Industrial) | — |
| Process Technology | CMOS EPROM, UV-erasable | — |
| 封裝 | 44-pin PQCC / PLCC-44 (J-lead) | 44-pin PLCC (J-lead) |
| 安裝類型 | Surface Mount (socket recommended for UV erasure) | — |
| Dedicated Inputs | 10 | — |
| I/O Pins | 22 | — |
| Programming Method | Altera EPLD programming algorithm / MAX+PLUS II legacy support | EPROM/UV-erase programmer (Altera Classic algorithm) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance not verified in scraped data] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Manufacturer (Original) | Altera (now Intel PSG) | — |
| Current Stocking Channel | Rochester Electronics (authorized aftermarket) | — |
| Device Family | — | Altera Classic EPLD |
| Part Number Base | — | EP910 |
| Logic Density | — | 450 usable gates |
| Maximum Pin-to-Pin Delay (tpd) | — | 35 ns |
| Maximum Toggle Frequency (fmax) | — | 28.6 MHz |
| 工作溫度範圍 | — | Industrial (LI suffix) |
| Technology | — | CMOS, UV-erasable |
| Output Polarity Control | — | Programmable XOR per macrocell |
| Flip-Flop Type | — | Selectable D/T/JK/SR per macrocell |
| TTL Compatibility | — | 100% TTL emulation |
| Compliance / EOL Status | — | Obsolete - last-time buy exhausted; second-source via Rochester Electronics |