EP910LI-35H vs EP910LI-35 比較
詳細並排比較 EP910LI-35H 由 Intel 與 EP910LI-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LI-35H | EP910LI-35 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | NRND |
| Family | Altera Classic EPLD (EP910) | Altera Classic EPLD |
| Logic Capacity | 900 usable gates | — |
| Macro Cells | 24 | — |
| Speed Grade (tPD) | 35 ns | — |
| Maximum Frequency | [DATA_NEEDED: fMAX] | — |
| Supply Voltage (VCC) | 5 V (±10%) | — |
| Technology | CMOS, UV-erasable EPROM cell | — |
| 封裝 | 44-pin PLCC (J-lead) | 44-pin PLCC (J-lead) |
| 工作溫度 | -40C to +85C (industrial) | -40 °C to +85 °C (Industrial) |
| Standby Current | [DATA_NEEDED: ICCSB] | — |
| Active Supply Current | [DATA_NEEDED: ICC] | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | unknown | — |
| Lead-Free Option (H suffix) | Yes (H suffix) | — |
| Device Series | — | EP910 |
| Usable Gates | — | 900 |
| Macrocells | — | 24 |
| Maximum User I/O Pins | — | 38 |
| Propagation Delay (t_PD) | — | 35 ns |
| Maximum Counter Frequency (f_CNT) | — | 76.9 MHz |
| 供應電壓 | — | 5 V (4.75 V to 5.25 V) |
| Process Technology | — | CMOS EPROM |
| Programming Technology | — | EPROM (UV-erasable) |
| Erase/Program Cycles | — | ≥100 |
| Lead Pitch | — | 1.27 mm |