EP910LI-50 vs EP910LI-15 比較
詳細並排比較 EP910LI-50 由 Altera 與 EP910LI-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LI-50 | EP910LI-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | NRND | 啟用中 |
| Family | Altera Classic EPLD | — |
| Macrocells | 24 | — |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 50 ns | — |
| Package Type | CERDIP-40 (L) | — |
| Package Pin Count | 40 | 44 terminals |
| Supply Voltage (VCC) | 5 V +/- 10% | — |
| 工作溫度 | -40C to +85C (industrial) | — |
| Technology | CMOS, UV-erasable EPROM | CMOS |
| Logic Blocks | Classic AND/OR array architecture | — |
| I/O Pins | [DATA_NEEDED: I/O pin count] | — |
| Programming Method | EPROM programmer (UV-erasable window) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Speed Grade Suffix | -50 (50 ns tPD) | — |
| Product Type | — | Programmable Logic Device (PLD) |
| Device Family | — | Altera Classic EPLD |
| Part Number | — | EP910LI-15 |
| Supply Voltage Range | — | 4.5 V to 5.5 V |
| Dedicated Inputs | — | 12 |
| Input/Output Lines | — | 24 |
| Total User-Signal Resources | — | 36 |
| Speed Grade | — | 15 ns |
| 工作溫度範圍 | — | -40 °C to +85 °C |
| 封裝 | — | 44-terminal J-lead ceramic chip carrier (PQCC44) |
| Package Mounting | — | Surface Mount |
| Dielectric/Construction | — | Ceramic |
| REACH Status | — | unknown |
| AEC-Q100 Status | — | not_applicable |
| Lead-Free Status | — | unknown |
| Halogen-Free Status | — | unknown |
| Conflict Minerals Status | — | unknown |