EP910PC-15 vs EP910PC-30 比較
詳細並排比較 EP910PC-15 由 Altera 與 EP910PC-30 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PC-15 | EP910PC-30 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Usable Gates | 900 | ~450 |
| Macrocells | 24 | 24 |
| Maximum Pin-to-Pin Delay (tpd) | 15 ns | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V ±10% |
| Supply Current (Icc) | 80 mA typical | — |
| Dedicated Inputs | 10 | — |
| Dedicated I/O Pins | 12 | — |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| 封裝 | 24-pin PDIP (PDIP-24, 0.300 inch) | PDIP-40 (plastic DIP, 0.6 inch) |
| 安裝類型 | Through-Hole | Through-hole DIP |
| Process Technology | CMOS, UV-erasable | — |
| Programming Method | Altera Logic Programmer card | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - EP910 is a legacy through-hole part, likely non-RoHS] | Non-compliant (contains lead, PDIP package) |
| MSL 等級 | Not applicable (through-hole) | — |
| Pin-to-Pin Propagation Delay (tPD) | — | 30 ns |
| Maximum Counter Frequency (fCNT) | — | 33.3 MHz |
| Logic Inputs | — | 36 dedicated |
| I/O Pins | — | 12 bidirectional |
| Logic Array Blocks (LABs) | — | 4 |
| Programming Technology | — | UV-erasable EPROM cell |
| TTL Emulation | — | 100% TTL-compatible |
| Power Dissipation | — | [DATA_NEEDED: power dissipation mW] |