EP910PC-20T vs EP910PI-15T 比較

詳細並排比較 EP910PC-20T 由 Altera 與 EP910PI-15T 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EP910PC-20T EP910PI-15T
品牌 Altera Altera
類別 FPGA & CPLD FPGA & CPLD
生命週期狀態 Unknown Obsolete
Device Type EPLD —
Family Classic EPLD Altera Classic EPLD (EP910 series)
Fabrication Technology CMOS —
Logic Integration 300 to 900 usable gates —
Logic Emulation 100% TTL emulation —
Application Function High-speed, low-power logic integration —
Programmable Device Class Erasable programmable logic device —
Device Family Altera Classic EPLD Family —
Speed Grade 20 ns —
Package Code PC —
Package Pin Count [DATA_NEEDED: package pin count] —
Package Dimensions [DATA_NEEDED: package dimensions] —
供應電壓 [DATA_NEEDED: operating supply voltage] 4.5 V to 5.5 V (5 V nominal)
工作溫度 [DATA_NEEDED: operating temperature range] [DATA_NEEDED: industrial/commercial temp range]
I/O Count [DATA_NEEDED: I/O count] —
Internal Logic Capacity 300 to 900 usable gates —
Supported Logic Integration Multiple PAL- and GAL-type devices —
Programming Interface [DATA_NEEDED: programming interface] —
Programming Voltage [DATA_NEEDED: programming voltage] —
Mounting Technology [DATA_NEEDED: mounting technology] —
RoHS 狀態 unknown [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP]
REACH Status unknown —
AEC-Q100 Qualification not_applicable —
Lead-Free Status unknown —
Halogen-Free Status unknown —
Product Type — Classic EPLD (Erasable Programmable Logic Device)
Macrocells — 24
Dedicated Inputs — 12
I/O Pins — 24
Logic Blocks — 6 LABs of 4 macrocells each (Classic architecture)
Propagation Delay (tPD) — 15 ns max (speed grade -15)
Technology — CMOS EEPROM (electrically erasable)
封裝 — 40-pin PDIP (Plastic DIP, R-PDIP-T40)
安裝類型 — Through-Hole
Output Drive Current — [DATA_NEEDED: per-pin DC output current, mA]
Programming — JEDEC-standard, serial/parallel programmer

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