EP910PI-20 vs EP910PI-20T 比較
詳細並排比較 EP910PI-20 由 Altera 與 EP910PI-20T 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PI-20 | EP910PI-20T |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Device Family | Altera Classic EPLD Family | — |
| Macrocells | 24 | — |
| Propagation Delay (tPD) | 20 ns | — |
| 封裝 | PDIP-40 (PI suffix) | PDIP-40 (PI) |
| 安裝類型 | Through-Hole | Through-Hole (DIP) |
| Supply Voltage (VCC) | 5 V (+/- 5%) | — |
| 工作溫度 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Technology | CMOS EPROM (UV-erasable windowed variants available) | CMOS EPROM (UV-erasable) |
| Configuration Method | Non-volatile EPROM (no boot PROM required) | — |
| Dedicated Inputs | 12 | — |
| Bidirectional I/O Pins | 24 | — |
| Maximum Counter Frequency | 125 MHz | — |
| Output Drive Current (IOL) | 24 mA (TTL-compatible) | — |
| Programmable Polarity | Yes (XOR gate per macrocell) | — |
| Macrocell Flip-Flop | Yes (D-type, programmable) | — |
| Power Dissipation | [DATA_NEEDED: typical power dissipation in mW] | — |
| Programming Interface | JEDEC file via Altera programming hardware | — |
| RoHS 狀態 | unknown | unknown |
| MIL-STD-883 Variant | EP910DM/883B (separate part number) | — |
| Family | — | Altera Classic EPLD |
| Device | — | EP910 |
| Number of Macrocells | — | 24 |
| Number of Usable Gates | — | [DATA_NEEDED: usable gate count] |
| Propagation Delay (tpd) | — | 20 ns |
| Maximum Toggle Frequency | — | 62.5 MHz |
| Number of Dedicated Inputs | — | 12 |
| Number of I/O Pins | — | 20 |
| 腳位數 | — | 40 |
| Programming | — | Standard EPROM programmer, JEDEC map |
| 生命週期狀態 | — | Not Recommended for New Designs (NRND) |