EP910PI-20 vs EP910PI-25T 比較
詳細並排比較 EP910PI-20 由 Altera 與 EP910PI-25T 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PI-20 | EP910PI-25T |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD Family | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 20 ns | — |
| 封裝 | PDIP-40 (PI suffix) | 40-pin PDIP (600-mil) |
| 安裝類型 | Through-Hole | Through-Hole (DIP) |
| Supply Voltage (VCC) | 5 V (+/- 5%) | 5 V |
| 工作溫度 | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Technology | CMOS EPROM (UV-erasable windowed variants available) | CMOS, UV-erasable EPROM |
| Configuration Method | Non-volatile EPROM (no boot PROM required) | — |
| Dedicated Inputs | 12 | — |
| Bidirectional I/O Pins | 24 | — |
| Maximum Counter Frequency | 125 MHz | — |
| Output Drive Current (IOL) | 24 mA (TTL-compatible) | — |
| Programmable Polarity | Yes (XOR gate per macrocell) | — |
| Macrocell Flip-Flop | Yes (D-type, programmable) | — |
| Power Dissipation | [DATA_NEEDED: typical power dissipation in mW] | — |
| Programming Interface | JEDEC file via Altera programming hardware | — |
| RoHS 狀態 | unknown | [DATA_NEEDED: RoHS compliance] |
| MIL-STD-883 Variant | EP910DM/883B (separate part number) | — |
| Family | — | Altera Classic EPLD Family |
| Equivalent Gates | — | 900 (SSI/MSI equivalent) |
| Maximum Inputs | — | 36 |
| Maximum Outputs | — | 24 |
| Propagation Delay (tpd) | — | 25 ns |
| Programming | — | UV-erasable |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Static Power | — | <100 mW (typical CMOS) |