EP910PI-25 vs EP910PI-30T 比較
詳細並排比較 EP910PI-25 由 Intel 與 EP910PI-30T 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PI-25 | EP910PI-30T |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device | EP910 | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 10 |
| I/O Pins | 24 | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Maximum Clock Frequency (fMAX) | 40 MHz | — |
| Supply Voltage (VCC) | 5 V nominal | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | 5 V CMOS (EPROM-based) | — |
| 封裝 | PDIP-40 (Plastic DIP) | — |
| 腳位數 | 40 | — |
| 安裝類型 | Through-Hole | Through-Hole |
| 工作溫度 | 0C to +70C (commercial) | -40 C to +85 C (industrial) |
| Programmability | UV-erasable (windowed) / one-time-programmable | — |
| RoHS 狀態 | Non-compliant (PDIP package) | [DATA_NEEDED: RoHS status] |
| Product Type | — | EPLD (Erasable Programmable Logic Device) |
| Usable Gates | — | 480 |
| Propagation Delay (tPD) | — | 30 ns |
| Register (Clock-to-Output) Delay | — | 20 ns |
| Technology | — | CMOS, UV-erasable (windowed ceramic) |
| Package Type | — | 40-pin PDIP (ceramic windowed) |
| Programming | — | Altera Classic device programmer / MAX+PLUS II flow |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |