EP910PI-35 vs EP910DC-35 比較
詳細並排比較 EP910PI-35 由 Rochester Electronics 與 EP910DC-35 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Rochester Electronics
EP910PI-35 - 24-Macrocell Classic EPLD, 35ns, PDIP-40 | Rochester/Altera
EP910PI-35 ✓ 啟用中規格比較
| 參數 | EP910PI-35 | EP910DC-35 |
|---|---|---|
| 品牌 | Rochester Electronics | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | Obsolete |
| Device Family | Altera Classic EPLD (EP910) | — |
| Logic Elements | 24 Macrocells | — |
| Usable Gates | 450 | 900 gates |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM cell |
| I/O Pins | 24 bidirectional | 24 |
| Dedicated Inputs | 12 | 12 |
| 封裝 | PDIP-40 (Plastic DIP, through-hole) | 40-pin CDIP (Ceramic DIP) with quartz window |
| Programming Method | Legacy Altera programming interface (pre-JTAG) | JEDEC fuse map via device programmer; UV erase |
| 工作溫度 | [DATA_NEEDED: operating temperature grade] | 0 °C to +70 °C (commercial) |
| Erasure Method | UV light (windowed variants) / One-time-programmable (this PI suffix) | — |
| RoHS 狀態 | unknown | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Device Type | — | UV-Erasable CMOS PLD (PAL-type) |
| Family | — | Classic EPLD EP910 |
| Architecture | — | PAL-type sum-of-products AND-OR array |
| Macrocells | — | 24 |
| Product Terms | — | 240 |
| Total Inputs | — | 36 |
| Propagation Delay (tpd) | — | 35 ns |
| 最大時脈頻率 | — | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |