EPC1213LC20 vs EPC1213PC8 比較
詳細並排比較 EPC1213LC20 由 Intel 與 EPC1213PC8 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC1213LC20 | EPC1213PC8 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | EEPROM | Memory ICs |
| 生命週期狀態 | Obsolete | Obsolete |
| 記憶體類型 | OTP Configuration PROM (Flash-based) | OTP Configuration PROM (EEPROM cell) |
| 記憶體容量 | 212 Kbit | 212 Kbit |
| 介面 | Serial (Altera FPGA configuration protocol) | Serial (4-wire: nCS, DCLK, DATA, OE) |
| Maximum Configuration Clock | 6 MHz | — |
| Supply Voltage (Core) | 5.0 V | — |
| I/O Voltage Tolerance | 3.3 V / 5.0 V | — |
| Programmability | One-Time Programmable (OTP) via IEEE 1149.1 JTAG | One-Time Programmable (OTP) |
| In-System Programmability | Yes (5.0 V and 3.3 V ISP) | — |
| Supported FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX | — |
| Compression Support | Yes (FPGA decompresses bitstream during load) | — |
| 工作溫度 | 0C to +70C (Commercial) | 0 °C to +70 °C (Commercial) |
| 封裝 | 20-PLCC (J-lead, 9x9 mm) | 8-Pin PDIP (R-PDIP-T8) |
| Package Code | QCCJ | — |
| 安裝類型 | Surface Mount | Through-Hole |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance status] | Compliant (post-lead-free Altera revision) |
| Configuration Mode Supported | — | FLEX/APEX FPP / PS serial |
| 最大時脈頻率 | — | 6 MHz |
| 供應電壓 | — | 3.0 V to 3.6 V |
| Programming Standard | — | IEEE Std 1532 / Jam STAPL |
| Standby Current | — | < 50 µA typical |
| 腳位數 | — | 8 |
| Lead-Free | — | Yes |
| JEDEC Package Code | — | R-PDIP-T8 |