EPC16QC-100T vs EPC16QC100DM 比較

詳細並排比較 EPC16QC-100T 由 Altera 與 EPC16QC100DM 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC16QC-100T EPC16QC100DM
品牌 Altera Intel
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete NRND
記憶體類型 Flash Configuration PROM (in-system programmable) Non-volatile Configuration PROM (NOR flash)
Memory Density 16 Mbit (2 Mbyte) 16 Mbit (2 Mbyte)
Supported FPGA Families Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K —
Configuration Data Width 8-bit or 16-bit (cascaded dual-device mode) —
Configuration Modes Serial (single device), Parallel (two cascaded devices) —
Data Compression Support Yes (35% to 55% bitstream reduction typical) —
JTAG / Boundary Scan IEEE 1149.1 compliant, in-system programmable —
供應電壓 3.3 V —
封裝 100-pin PQFP (20 x 14 mm), 0.65 mm pitch 100-pin PQFP (QFPA)
工作溫度 [DATA_NEEDED: Operating temperature range] —
Cascade Interface nCE / nOE handshake for multi-device chains —
Programming Interface JTAG (IEEE 1149.1) and serial —
Endurance [DATA_NEEDED: Program/erase cycle rating] —
Data Retention [DATA_NEEDED: Data retention specification] [DATA_NEEDED: data retention years]
RoHS 狀態 unknown —
Lead-Free unknown —
MSL 等級 [DATA_NEEDED: Moisture sensitivity level] [DATA_NEEDED: MSL rating]
安裝類型 Surface Mount —
Configuration Interface — Serial (SPI-compatible, Altera FPP mode)
Core Supply Voltage (VCC) — 3.0 V to 3.6 V
I/O Voltage (VIO) — 2.5 V / 3.3 V selectable
Output Voltage (VPP) — 1.8 V / 2.5 V / 3.3 V selectable
Maximum DCLK Frequency — 40 MHz
Cascadable — Yes (multi-device daisy chain via nCASC)
In-System Programming — Yes (IEEE 1532 / JTAG)
Program/Erase Cycles — [DATA_NEEDED: program/erase cycle endurance]
工作溫度範圍 — -40 C to +85 C (industrial)
Package Code — Q100 + DM suffix
Lead-Free / RoHS — [DATA_NEEDED: lead-free status]
Compatible FPGA Families — Stratix, Cyclone, APEX, ACEX

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