EPC16QC-100T vs EPC16QC100II 比較

詳細並排比較 EPC16QC-100T 由 Altera 與 EPC16QC100II 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC16QC-100T EPC16QC100II
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete NRND
記憶體類型 Flash Configuration PROM (in-system programmable) FPGA Configuration PROM (Flash-based)
Memory Density 16 Mbit (2 Mbyte) 16 Mbit
Supported FPGA Families Stratix, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, FLEX 8000, Cyclone
Configuration Data Width 8-bit or 16-bit (cascaded dual-device mode) —
Configuration Modes Serial (single device), Parallel (two cascaded devices) —
Data Compression Support Yes (35% to 55% bitstream reduction typical) —
JTAG / Boundary Scan IEEE 1149.1 compliant, in-system programmable —
供應電壓 3.3 V —
封裝 100-pin PQFP (20 x 14 mm), 0.65 mm pitch 100-pin PQFP (Plastic Quad Flat Pack)
工作溫度 [DATA_NEEDED: Operating temperature range] -40C to +85C (Industrial)
Cascade Interface nCE / nOE handshake for multi-device chains —
Programming Interface JTAG (IEEE 1149.1) and serial —
Endurance [DATA_NEEDED: Program/erase cycle rating] —
Data Retention [DATA_NEEDED: Data retention specification] —
RoHS 狀態 unknown Compliant
Lead-Free unknown —
MSL 等級 [DATA_NEEDED: Moisture sensitivity level] 3 (per JEDEC J-STD-020)
安裝類型 Surface Mount —
Configuration Mode — FPP / PSA (Fast Passive Parallel / Passive Serial Asynchronous)
Programmability — In-System Programmable via IEEE 1149.1 (JTAG)
Cascade Support — Yes (multi-PROM cascading supported)
Core Supply Voltage — 3.3 V
I/O Tolerance — 5 V tolerant configuration pins
Package Dimensions — 20 mm x 14 mm, 0.5 mm pitch
Lead Finish — Matte Tin (lead-free)
Configuration Pins — DCLK, DATA[0..n], nCONFIG, nSTATUS, CONF_DONE, OE
Compression Support — Yes (reduces on-PROM footprint vs uncompressed bitstream)

資料表與資源

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